VHDL Interfaces

This repository provides generic VHDL-2019 Interfaces (mode views) descriptions of commonly used interfaces like UART, I²C, …, AXI, WishBone, Avalon, …, MII, GMII, SGMII, …

Interfaces are defined in 2 stages (see example to the right):

1. Define all necessary signals in a VHDL record type. If interfaces are more complicated and grouped in sub-interfaces, records can be nested. If a record sub-element is an array, usually these sub-elements are unconstrained, thus they can be constrained later.

2. Define a view, which defines directions (modes) for each record sub-element. Usually, the reverse view is created by creating an alias using the 'converse attribute.

library IEEE;
use     IEEE.std_logic_1164.all;

package JTAG is
   type JTAG_Interface is record
      TCK  : std_logic;  -- Test Clock
      TRST : std_logic;  -- Test Reset
      TMS  : std_logic;  -- Test Mode Select
      TDI  : std_logic;  -- Test Data In
      TDO  : std_logic;  -- Test Data Out
   end record;

   view JTAG_DeviceView of JTAG_Interface is
      TCK  : in;
      TRST : in;
      TMS  : in;
      TDI  : in;
      TDO  : out;
   end view;
   alias JTAG_TesterView is JTAG_DeviceView'converse;
end package;

Supported Interfaces

AMBA

• AXI - Advanced eXtensible Interface:

  • AXI4 (Full)

  • AXI4-Lite

  • AXI4-Stream

Avalon

• Avalon-MM

• Avalon-ST

WishBone

• OpenCores/Silicore

  • WishBone B.3

  • WishBone B.4

• FOSSi Foundation

  • WishBone Interconnect

PoC Library

• CSE - Command-Status-Error

• FIFO

I/O

• BiSS - Bidirectional/Serial/Synchronous

• I²C - Inter-Integrated Circuit

• I²S - Inter-Integrated Circuit Sound

• JTAG

• SPI - Serial Peripheral Interface

• UART - universal asynchronous receiver-transmitter

PCI Express

• PCI Express

Network

• Ethernet

  • MII

  • RMII

  • GMII

  • RGMII

  • SGMII

• Cages:

  • SFP

  • QSFP

Video

• MIPI:

  • C-PHY

  • D-PHY

  • M-PHY

• VESA

  • VGA

Adopters

• Paebbels/BigDesign

• … (Contact the maintainer to get listed.)

Tests

• VHDL-2019 syntax checked by NVC.
  See test results.

Contributors

• Patrick Lehmann (Maintainer)

• Parham Soltani

• and more…

License

This VHDL library (source code) is licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).