axi4_to_AXI4Lite

Instantiation

Todo

needs documentation

FIFO : entity PoC.axi4_to_AXI4Lite
port map (
  Clock   => Clock,
  Reset   => Reset,

  In_m2s  => Source_m2s,
  In_s2m  => Source_s2m

  Out_m2s => Config_m2s,
  Out_s2m => Config_s2m
);

Interface

Generics

RESPONSE_FIFO_DEPTH

Name:: RESPONSE_FIFO_DEPTH
Type:: positive
Default Value:: 16
Description:: tbd

Ports

Clock

Name:: Clock
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: Clock

Reset

Name:: Reset
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: synchronous high-active reset

In_m2s

Name:: In_m2s
Type:: axi4.T_AXI4_Bus_m2s
Mode:: in
Default Value:: — — — —
Description:: AXI4 manager to subordinate signals.

In_s2m

Name:: In_s2m
Type:: axi4.T_AXI4_Bus_s2m
Mode:: out
Default Value:: — — — —
Description:: AXI4 subordinate to manager signals.

Out_m2s

Name:: Out_m2s
Type:: axi4lite.T_AXI4Lite_Bus_m2s
Mode:: out
Default Value:: — — — —
Description:: AXI4-Lite manager to subordinate signals.

Out_s2m

Name:: Out_s2m
Type:: axi4lite.T_AXI4Lite_Bus_s2m
Mode:: in
Default Value:: — — — —
Description:: AXI4-Lite subordinate to manager signals.

Configuration

Todo

tbd

Use in

tbd