axi4lite_GitVersionRegister

Current version of this version Reg is 1. Use this tcl script for Vivado synth-pre-tcl: [set_BuildVersion.tcl](/uploads/9fdf1898a1797857e11889134c5179d0/set_BuildVersion.tcl)

Based on axi4lite_Register

Instantiation

Simple Register

Todo

needs documentation

Version : entity PoC.axi4lite_GitVersionRegister
port map (
  Clock        => Clock,
  Reset        => Reset,

  AXI4Lite_m2s => VersionRegister_m2s,
  AXI4Lite_s2m => VersionRegister_s2m
);

AMD/Xilinx Extensions

Todo

needs documentation

Version : entity PoC.axi4lite_GitVersionRegister
generic map (
  INCLUDE_XIL_DNA       => true,
  INCLUDE_XIL_USR_EFUSE => true
)
port map (
  Clock        => Clock,
  Reset        => Reset,

  AXI4Lite_m2s => VersionRegister_m2s,
  AXI4Lite_s2m => VersionRegister_s2m
);

Interface

Generics

VERSION_FILE_NAME

Name:

VERSION_FILE_NAME

Type:

string

Default Value:

— — — —

Description:

Path to the Version-mem-file created by set_BuildVersion.tcl. Relative to constant MY_PROJECT_DIR in src/PoC/my_project.vhdl

HEADER_FILE_NAME

Name:

HEADER_FILE_NAME

Type:

string

Default Value:

— — — —

Description:

If csv-file with all register spaces is needed, put here the name/path of csv-file. Relative to constant MY_PROJECT_DIR in src/PoC/my_project.vhdl

INCLUDE_XIL_DNA

Name:

INCLUDE_XIL_DNA

Type:

boolean

Default Value:

— — — —

Description:

Includes Xilinx-DNA-Port. Working for 7-Series and US/US+ Devices. Note: 7-Series has 32 times this “unique” ID.

INCLUDE_XIL_USR_EFUSE

Name:

INCLUDE_XIL_USR_EFUSE

Type:

boolean

Default Value:

— — — —

Description:

Includes Usr-EFuse. Currently not Implemented

USER_ID

Name:

USER_ID

Type:

std_logic_vector(31 downto 0)

Default Value:

— — — —

Description:

96bit ID, which can be set through PL in synthesis.

Ports

Clock

Name:

Clock

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

Clock

Reset

Name:

Reset

Type:

std_logic

Mode:

in

Default Value:

— — — —

Description:

synchronous high-active reset

AXI4Lite_m2s

Name:

AXI4Lite_m2s

Type:

axi4lite.T_AXI4Lite_Bus_m2s

Mode:

in

Default Value:

— — — —

Description:

AXI4-Lite manager to subordinate signals.

AXI4Lite_s2m

Name:

AXI4Lite_s2m

Type:

axi4lite.T_AXI4Lite_Bus_s2m

Mode:

out

Default Value:

— — — —

Description:

AXI4-Lite subordinate to manager signals.

Configuration

User defined Word

Todo

tbd

Register Map

All registers are read-only. Version Register should always start with offset 0x80000000 (First PL Address).

Tip

The version register should be the first address in the address space (e.g., 0x8000_0000), thus a software can check what PL firmware is active and if this firmware is compatible to the currently running software version.

Offset

Name

Description

0x000

Common.BuildDate

31:24 Day
23:16 Month
15:0 Year

0x004

Common.NumberModule_VersionOfVersionReg

31:8 Reserved
7:0 Version-of-Version-Reg (1)

0x008

Common.VivadoVersion

31:16 Major
15:8 Minor
7:0 Patch

0x00C

Common.ProjektName

String Project-Name (20 bytes)

0x020

Top.Version

31:24 Major
23:16 Minor
15:8 Patch
7:2 Commits-to-Tag(dev-build)
1 Dirty_untracked
0 Dirty_modified

0x024

Top.GitHash

Git-Hash 20Bytes. Endianess is reversed in the registers. The order of the registers is reversed as well.

0x038

Top.GitDate

Commit-Date: 31:24 Day
23:16 Month
15:0 Year

0x03C

Top.GitTime

Commit-Time: 31:24 Hour
23:16 Min
15:8 Sec
7:0 Time-Zone as signed

0x040

Top.BranchName_Tag

Branch-Name 64Byte

0x080

Top.GitURL

Git-URL starting after gitlab.plc2.de/ (128Byte)

0x100

UID.UID

Only present if INCLUDE_XIL_DNA is enabled (16Byte)
For US/US+ lower 96 bit valid, for Series-7 64 bit valid

0x110

UID.User_eFuse

Only present if INCLUDE_XIL_USR_EFUSE is enabled

0x114

UID.User_ID

96-bit User_ID set by PL

Driver

Bare Metal

Todo

needs to be documented

Linux Kernel Driver

Attention

under development