axi4stream_FIFO_cdc

Instantiation

Todo

needs documentation

FIFO : entity PoC.axi4stream_FIFO_cdc
generic map (
  TRANSACTIONS => 64
)
port map (
  In_Clock  => Source_Clock,
  In_Reset  => Source_Reset,
  In_m2s    => Source_m2s,
  In_s2m    => Source_s2m.

  Out_Clock => FIFO_Clock,
  Out_Reset => FIFO_Reset,
  Out_m2s   => FIFO_m2s,
  Out_s2m   => FIFO_s2m
);

Interface

Generics

TRANSACTIONS

Name:: TRANSACTIONS
Type:: positive
Default Value:: 2
Description:: tbd

DATA_REG

Name:: DATA_REG
Type:: boolean
Default Value:: false
Description:: tbd

OUTPUT_REG

Name:: OUTPUT_REG
Type:: boolean
Default Value:: false
Description:: tbd

Ports

In_Clock

Name:: In_Clock
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: Clock

In_Reset

Name:: In_Reset
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: synchronous high-active reset

In_m2s

Name:: In_m2s
Type:: axi4stream.T_AXI4stream_Bus_m2s
Mode:: in
Default Value:: — — — —
Description:: AXI4-stream manager to subordinate signals.

In_s2m

Name:: In_s2m
Type:: axi4stream.T_AXI4stream_Bus_s2m
Mode:: out
Default Value:: — — — —
Description:: AXI4-stream subordinate to manager signals.

Out_Clock

Name:: Out_Clock
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: Clock

Out_Reset

Name:: Out_Reset
Type:: std_logic
Mode:: in
Default Value:: — — — —
Description:: synchronous high-active reset

Out_m2s

Name:: Out_m2s
Type:: axi4stream.T_AXI4stream_Bus_m2s
Mode:: out
Default Value:: — — — —
Description:: AXI4-stream manager to subordinate signals.

Out_s2m

Name:: Out_s2m
Type:: axi4stream.T_AXI4stream_Bus_s2m
Mode:: in
Default Value:: — — — —
Description:: AXI4-stream subordinate to manager signals.

Configuration

Todo

tbd

Use in

tbd