Coverage for pyVHDLModel/Expression.py: 99%
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32"""
33This module contains parts of an abstract document language model for VHDL.
35All declarations for literals, aggregates, operators forming an expressions.
36"""
37from enum import Flag
38from typing import Tuple, List, Iterable, Union, ClassVar, Optional as Nullable
40from pyTooling.Decorators import export, readonly
42from pyVHDLModel.Base import ModelEntity, Direction, Range
43from pyVHDLModel.Symbol import Symbol, SubtypeSymbol
46ExpressionUnion = Union[
47 'BaseExpression',
48 'QualifiedExpression',
49 'FunctionCall',
50 'TypeConversion',
51 # ConstantOrSymbol, TODO: ObjectSymbol
52 'Literal',
53]
56@export
57class BaseExpression(ModelEntity):
58 """
59 Represents the base-class of all expressions.
61 .. seealso::
63 * :class:`Literal <pyVHDLModel.Expression.Literal>`
64 * :class:`Unary expression <pyVHDLModel.Expression.UnaryExpression>`
65 * :class:`Binary expression <pyVHDLModel.Expression.BinaryExpression>`
66 * :class:`Qualified expression <pyVHDLModel.Expression.QualifiedExpression>`
67 * :class:`Ternary expression <pyVHDLModel.Expression.TernaryExpression>`
68 * :class:`Function call <pyVHDLModel.Expression.FunctionCall>`
69 * :class:`Allocation <pyVHDLModel.Expression.Allocation>`
70 * :class:`Aggregate <pyVHDLModel.Expression.Aggregate>`
71 """
74@export
75class Literal(BaseExpression):
76 """
77 Represents the base-class of all literals.
79 A literal is an expression denoting a value written directly in the source.
81 .. seealso::
83 * :class:`Null literal <pyVHDLModel.Expression.NullLiteral>`
84 * :class:`Enumeration literal <pyVHDLModel.Expression.EnumerationLiteral>`
85 * :class:`Numeric literal <pyVHDLModel.Expression.NumericLiteral>`
86 * :class:`Character literal <pyVHDLModel.Expression.CharacterLiteral>`
87 * :class:`String literal <pyVHDLModel.Expression.StringLiteral>`
88 * :class:`Bit string literal <pyVHDLModel.Expression.BitStringLiteral>`
89 """
92@export
93class NullLiteral(Literal):
94 """
95 Represents a ``null`` literal.
97 A null literal denotes the null value of an access type.
99 .. admonition:: Example
101 .. code-block:: VHDL
103 p := null;
104 -- ^^^^ <- the literal
105 """
106 def __str__(self) -> str:
107 """
108 Formats the null literal.
110 **Format:** ``null``
112 :returns: Formatted null literal.
113 """
114 return "null"
117@export
118class EnumerationLiteral(Literal):
119 """
120 Represents an enumeration literal.
122 The literal's name is available as :data:`Value`.
124 .. admonition:: Example
126 .. code-block:: VHDL
128 st <= Idle;
129 -- ^^^^ <- Value
130 """
131 _value: str #: The enumeration literal's name.
133 def __init__(self, value: str, parent: Nullable[ModelEntity] = None) -> None:
134 """
135 Initializes an enumeration literal.
137 :param value: The enumeration literal's name.
138 :param parent: The parent model entity of this entity.
139 """
140 super().__init__(parent)
142 self._value = value
144 @readonly
145 def Value(self) -> str:
146 """
147 Read-only property to access the value (:attr:`_value`).
149 :returns: The value.
150 """
151 return self._value
153 def __str__(self) -> str:
154 """
155 Formats the enumeration literal.
157 **Format:** ``idle``
159 :returns: Formatted enumeration literal.
160 """
161 return self._value
164@export
165class NumericLiteral(Literal):
166 """
167 Represents the base-class of all numeric literals.
169 Integer, floating-point and physical literals are numeric.
171 .. seealso::
173 * :class:`Integer literal <pyVHDLModel.Expression.IntegerLiteral>`
174 * :class:`Floating point literal <pyVHDLModel.Expression.FloatingPointLiteral>`
175 * :class:`Physical literal <pyVHDLModel.Expression.PhysicalLiteral>`
176 """
179@export
180class IntegerLiteral(NumericLiteral):
181 """
182 Represents an integer literal.
184 The literal's value is available as :data:`Value`.
186 .. admonition:: Example
188 .. code-block:: VHDL
190 res := a + 42;
191 -- ^^ <- Value
192 """
193 _value: int #: The literal's integer value.
195 def __init__(self, value: int) -> None:
196 """
197 Initializes an integer literal.
199 :param value: The literal's integer value.
200 """
201 super().__init__()
202 self._value = value
204 @readonly
205 def Value(self) -> int:
206 """
207 Read-only property to access the value (:attr:`_value`).
209 :returns: The value.
210 """
211 return self._value
213 def __str__(self) -> str:
214 """
215 Formats the integer literal.
217 **Format:** ``42``
219 :returns: Formatted integer literal.
220 """
221 return str(self._value)
224@export
225class FloatingPointLiteral(NumericLiteral):
226 """
227 Represents a floating-point literal.
229 The literal's value is available as :data:`Value`.
231 .. admonition:: Example
233 .. code-block:: VHDL
235 r <= 3.14;
236 -- ^^^^ <- Value
237 """
238 _value: float #: The literal's floating-point value.
240 def __init__(self, value: float) -> None:
241 """
242 Initializes a floating-point literal.
244 :param value: The literal's floating-point value.
245 """
246 super().__init__()
247 self._value = value
249 @readonly
250 def Value(self) -> float:
251 """
252 Read-only property to access the value (:attr:`_value`).
254 :returns: The value.
255 """
256 return self._value
258 def __str__(self) -> str:
259 """
260 Formats the floating-point literal.
262 **Format:** ``3.5``
264 :returns: Formatted floating-point literal.
265 """
266 return str(self._value)
269@export
270class PhysicalLiteral(NumericLiteral):
271 """
272 Represents the base-class of all physical literals.
274 A physical literal combines a numeric value with a unit name (:data:`UnitName`).
276 .. admonition:: Example
278 .. code-block:: VHDL
280 t <= 10 ns;
281 -- ^^ <- the value
282 -- ^^ <- UnitName
284 .. seealso::
286 * :class:`Physical integer literal <pyVHDLModel.Expression.PhysicalIntegerLiteral>`
287 * :class:`Physical floating literal <pyVHDLModel.Expression.PhysicalFloatingLiteral>`
288 """
289 _unitName: str #: The name of the physical unit the value is given in.
291 def __init__(self, unitName: str) -> None:
292 """
293 Initializes a physical literal.
295 :param unitName: The name of the physical unit the value is given in.
296 """
297 super().__init__()
298 self._unitName = unitName
300 @readonly
301 def UnitName(self) -> str:
302 """
303 Read-only property to access the unit name (:attr:`_unitName`).
305 :returns: The unit name.
306 """
307 return self._unitName
309 def __str__(self) -> str:
310 """
311 Formats the physical literal.
313 **Format:** ``10 ns``
315 :returns: Formatted physical literal.
316 """
317 return f"{self._value} {self._unitName}"
320@export
321class PhysicalIntegerLiteral(PhysicalLiteral):
322 """
323 Represents a physical literal with an integer value.
325 Value (:data:`Value`) and unit name (:data:`UnitName`) are available separately.
327 .. admonition:: Example
329 .. code-block:: VHDL
331 t <= 10 ns;
332 -- ^^ <- Value
333 -- ^^ <- UnitName
334 """
335 _value: int #: The literal's integer value, in units of :attr:`_unitName`.
337 def __init__(self, value: int, unitName: str) -> None:
338 """
339 Initializes a physical literal with an integer value.
341 :param value: The literal's integer value, in units of :attr:`_unitName`.
342 :param unitName: The name of the physical unit the value is given in.
343 """
344 super().__init__(unitName)
345 self._value = value
347 @readonly
348 def Value(self) -> int:
349 """
350 Read-only property to access the value (:attr:`_value`).
352 :returns: The value.
353 """
354 return self._value
357@export
358class PhysicalFloatingLiteral(PhysicalLiteral):
359 """
360 Represents a physical literal with a floating-point value.
362 Value (:data:`Value`) and unit name (:data:`UnitName`) are available separately.
364 .. admonition:: Example
366 .. code-block:: VHDL
368 t <= 1.5 ns;
369 -- ^^^ <- Value
370 -- ^^ <- UnitName
371 """
372 _value: float #: The literal's floating-point value, in units of :attr:`_unitName`.
374 def __init__(self, value: float, unitName: str) -> None:
375 """
376 Initializes a physical literal with a floating-point value.
378 :param value: The literal's floating-point value, in units of :attr:`_unitName`.
379 :param unitName: The name of the physical unit the value is given in.
380 """
381 super().__init__(unitName)
382 self._value = value
384 @readonly
385 def Value(self) -> float:
386 """
387 Read-only property to access the value (:attr:`_value`).
389 :returns: The value.
390 """
391 return self._value
394@export
395class CharacterLiteral(Literal):
396 """
397 Represents a character literal.
399 The literal's character is available as :data:`Value`.
401 .. admonition:: Example
403 .. code-block:: VHDL
405 ch <= 'a';
406 -- ^^^ <- Value
407 """
408 _value: str #: The literal's character value.
410 def __init__(self, value: str) -> None:
411 """
412 Initializes a character literal.
414 :param value: The literal's character value.
415 """
416 super().__init__()
417 self._value = value
419 @readonly
420 def Value(self) -> str:
421 """
422 Read-only property to access the value (:attr:`_value`).
424 :returns: The value.
425 """
426 return self._value
428 def __str__(self) -> str:
429 """
430 Formats the character literal.
432 **Format:** ``a``
434 :returns: Formatted character literal.
435 """
436 return str(self._value)
439@export
440class StringLiteral(Literal):
441 """
442 Represents a string literal.
444 The literal's text is available as :data:`Value`.
446 .. admonition:: Example
448 .. code-block:: VHDL
450 txt <= "text";
451 -- ^^^^^^ <- Value
452 """
453 _value: str #: The literal's string value, without the enclosing double quotes.
455 def __init__(self, value: str) -> None:
456 """
457 Initializes a string literal.
459 :param value: The literal's string value, without the enclosing double quotes.
460 """
461 super().__init__()
462 self._value = value
464 @readonly
465 def Value(self) -> str:
466 """
467 Read-only property to access the value (:attr:`_value`).
469 :returns: The value.
470 """
471 return self._value
473 def __str__(self) -> str:
474 """
475 Formats the string literal.
477 **Format:** ``"hello"``
479 :returns: Formatted string literal.
480 """
481 return "\"" + self._value + "\""
484@export
485class BitStringBase(Flag):
486 """
487 Represents the base of a bit string literal: binary, octal, decimal or hexadecimal.
488 """
489 NoBase = 0
490 Binary = 2
491 Octal = 8
492 Decimal = 10
493 Hexadecimal = 16
494 Unsigned = 32
495 Signed = 64
498@export
499class BitStringLiteral(Literal):
500 """
501 Represents the base-class of all bit string literals.
503 Besides the literal as written (:data:`Value`), the bits are available in binary form
504 (:data:`BinaryValue`, :data:`Bits`), together with the literal's length (:data:`Length`) and
505 whether it is signed (:data:`IsSigned`).
507 .. admonition:: Example
509 .. code-block:: VHDL
511 res := b"10100000";
512 -- ^^^^^^^^^^^ <- Value
514 .. seealso::
516 * :class:`Binary bit string literal <pyVHDLModel.Expression.BinaryBitStringLiteral>`
517 * :class:`Octal bit string literal <pyVHDLModel.Expression.OctalBitStringLiteral>`
518 * :class:`Decimal bit string literal <pyVHDLModel.Expression.DecimalBitStringLiteral>`
519 * :class:`Hexadecimal bit string literal <pyVHDLModel.Expression.HexadecimalBitStringLiteral>`
520 """
521 _base: ClassVar[BitStringBase] = BitStringBase.NoBase #: The base this literal is written in.
523 _value: str #: The literal as written in the source, without the enclosing double quotes.
524 _binaryValue: str #: The literal's value expanded to base 2, one character per bit.
525 _bits: int #: The number of bits the literal represents.
526 _length: Nullable[int] #: The explicitly given length, or ``None`` if the literal has no length specification.
527 _isSigned: Nullable[bool] #: ``True`` if signed, ``False`` if unsigned, ``None`` if unspecified.
529 def __init__(self, value: str, length: Nullable[int] = None, isSigned: Nullable[bool] = None) -> None:
530 """
531 Initializes a bit string literal.
533 :param value: The literal as written in the source, without the enclosing double quotes.
534 :param length: The explicitly given length, or ``None`` if the literal has no length specification.
535 :param isSigned: ``True`` if signed, ``False`` if unsigned, ``None`` if unspecified.
536 """
537 super().__init__()
538 self._value = value
539 self._length = length
540 self._isSigned = isSigned
542 self._binaryValue = None
543 self._bits = None
545 @readonly
546 def Value(self) -> str:
547 """
548 Read-only property to access the value (:attr:`_value`).
550 :returns: The value.
551 """
552 return self._value
554 @readonly
555 def BinaryValue(self) -> str:
556 """
557 Read-only property to access the binary value (:attr:`_binaryValue`).
559 :returns: The binary value.
560 """
561 return self._binaryValue
563 @readonly
564 def Bits(self) -> Nullable[int]:
565 """
566 Read-only property to access the bits (:attr:`_bits`).
568 :returns: The bits, or ``None`` if not set.
569 """
570 return self._bits
572 @readonly
573 def Length(self) -> Nullable[int]:
574 """
575 Read-only property to access the length (:attr:`_length`).
577 :returns: The length, or ``None`` if not set.
578 """
579 return self._length
581 @readonly
582 def IsSigned(self) -> Nullable[bool]:
583 """
584 Check if the bit string literal is signed (:attr:`_isSigned`).
586 :returns: ``True``, if the literal is signed; ``None``, if unspecified.
587 """
588 return self._isSigned
590 def __str__(self) -> str:
591 """
592 Formats the bit string literal.
594 **Format:** ``8ub"10100000"``
596 The length and the signedness marker (``s``/``u``) are omitted when unspecified.
598 :returns: Formatted bit string literal.
599 """
600 signed = "" if self._isSigned is None else "s" if self._isSigned is True else "u"
601 if self._base is BitStringBase.NoBase: 601 ↛ 602line 601 didn't jump to line 602 because the condition on line 601 was never true
602 base = ""
603 elif self._base is BitStringBase.Binary:
604 base = "b"
605 elif self._base is BitStringBase.Octal:
606 base = "o"
607 elif self._base is BitStringBase.Decimal:
608 base = "d"
609 elif self._base is BitStringBase.Hexadecimal: 609 ↛ 611line 609 didn't jump to line 611 because the condition on line 609 was always true
610 base = "x"
611 length = "" if self._length is None else str(self._length)
612 return length + signed + base + "\"" + self._value + "\""
615@export
616class BinaryBitStringLiteral(BitStringLiteral):
617 """
618 Represents a bit string literal written in base 2.
620 .. admonition:: Example
622 .. code-block:: VHDL
624 res := b"10100000";
625 -- ^^^^^^^^^^^ <- Value
626 """
627 _base: ClassVar[BitStringBase] = BitStringBase.Binary #: The base this literal is written in.
630@export
631class OctalBitStringLiteral(BitStringLiteral):
632 """
633 Represents a bit string literal written in base 8.
635 Each digit contributes three bits.
637 .. admonition:: Example
639 .. code-block:: VHDL
641 nine := o"240";
642 -- ^^^^^^ <- Value
643 """
644 _base: ClassVar[BitStringBase] = BitStringBase.Octal #: The base this literal is written in.
647@export
648class DecimalBitStringLiteral(BitStringLiteral):
649 """
650 Represents a bit string literal written in base 10.
652 .. admonition:: Example
654 .. code-block:: VHDL
656 res := d"160";
657 -- ^^^^^^ <- Value
658 """
659 _base: ClassVar[BitStringBase] = BitStringBase.Decimal #: The base this literal is written in.
662@export
663class HexadecimalBitStringLiteral(BitStringLiteral):
664 """
665 Represents a bit string literal written in base 16.
667 Each digit contributes four bits.
669 .. admonition:: Example
671 .. code-block:: VHDL
673 res := x"A0";
674 -- ^^^^^ <- Value
675 """
676 _base: ClassVar[BitStringBase] = BitStringBase.Hexadecimal #: The base this literal is written in.
679@export
680class ParenthesisExpression: #(Protocol):
681 """
682 Represents the base-class of expressions wrapped in parentheses.
684 The operand is available as :data:`Operand`.
686 .. seealso::
688 * :class:`Sub expression <pyVHDLModel.Expression.SubExpression>`
689 * :class:`Qualified expression <pyVHDLModel.Expression.QualifiedExpression>`
690 """
691 __slots__ = () # FIXME: use ExtendedType?
693 @readonly
694 def Operand(self) -> ExpressionUnion:
695 """
696 Read-only property to return the operand. A parenthesis expression has none of its own.
698 :returns: The operand.
699 """
700 return None
703@export
704class UnaryExpression(BaseExpression):
705 """
706 Represents the base-class of all unary expressions.
708 The operand is available as :data:`Operand`.
709 """
711 _FORMAT: ClassVar[Tuple[str, str]] #: The operator's string representation as (prefix, suffix) around the operand.
712 _operand: ExpressionUnion #: The expression the operator is applied to.
714 def __init__(self, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
715 """
716 Initializes a unary expression.
718 :param operand: The expression the operator is applied to.
719 :param parent: The parent model entity of this entity.
720 """
721 super().__init__(parent)
723 self._operand = operand
724 operand.Parent = self
726 @readonly
727 def Operand(self) -> ExpressionUnion:
728 """
729 Read-only property to access the operand (:attr:`_operand`).
731 :returns: The operand.
732 """
733 return self._operand
735 def __str__(self) -> str:
736 """
737 Formats the unary expression.
739 **Format:** ``not operand``
741 :returns: Formatted unary expression.
742 """
743 return f"{self._FORMAT[0]}{self._operand!s}{self._FORMAT[1]}"
746@export
747class NegationExpression(UnaryExpression):
748 """
749 Represents a negation (unary minus) expression.
751 The operand is available as :data:`Operand`.
753 .. admonition:: Example
755 .. code-block:: VHDL
757 res := - operand;
758 -- ^^^^^^^^^ <- the expression
759 -- ^^^^^^^ <- Operand
760 """
761 _FORMAT: ClassVar[Tuple[str, str]] = ("-", "")
764@export
765class IdentityExpression(UnaryExpression):
766 """
767 Represents an identity (unary plus) expression.
769 The operand is available as :data:`Operand`.
771 .. admonition:: Example
773 .. code-block:: VHDL
775 res := + operand;
776 -- ^^^^^^^^^ <- the expression
777 -- ^^^^^^^ <- Operand
778 """
779 _FORMAT: ClassVar[Tuple[str, str]] = ("+", "")
782@export
783class InverseExpression(UnaryExpression):
784 """
785 Represents a logical inversion expression (``not``).
787 The operand is available as :data:`Operand`.
789 .. admonition:: Example
791 .. code-block:: VHDL
793 res := not operand;
794 -- ^^^^^^^^^^^ <- the expression
795 -- ^^^^^^^ <- Operand
796 """
797 _FORMAT: ClassVar[Tuple[str, str]] = ("not ", "")
800@export
801class UnaryAndExpression(UnaryExpression):
802 """
803 Represents a ``and`` reduction expression.
805 A reduction operator folds all elements of an array into a single value.
806 The operand is available as :data:`Operand`.
808 .. admonition:: Example
810 .. code-block:: VHDL
812 res := and operand;
813 -- ^^^^^^^^^^^ <- the expression
814 -- ^^^^^^^ <- Operand
815 """
816 _FORMAT: ClassVar[Tuple[str, str]] = ("and ", "")
819@export
820class UnaryNandExpression(UnaryExpression):
821 """
822 Represents a ``nand`` reduction expression.
824 A reduction operator folds all elements of an array into a single value.
825 The operand is available as :data:`Operand`.
827 .. admonition:: Example
829 .. code-block:: VHDL
831 res := nand operand;
832 -- ^^^^^^^^^^^^ <- the expression
833 -- ^^^^^^^ <- Operand
834 """
835 _FORMAT: ClassVar[Tuple[str, str]] = ("nand ", "")
838@export
839class UnaryOrExpression(UnaryExpression):
840 """
841 Represents a ``or`` reduction expression.
843 A reduction operator folds all elements of an array into a single value.
844 The operand is available as :data:`Operand`.
846 .. admonition:: Example
848 .. code-block:: VHDL
850 res := or operand;
851 -- ^^^^^^^^^^ <- the expression
852 -- ^^^^^^^ <- Operand
853 """
854 _FORMAT: ClassVar[Tuple[str, str]] = ("or ", "")
857@export
858class UnaryNorExpression(UnaryExpression):
859 """
860 Represents a ``nor`` reduction expression.
862 A reduction operator folds all elements of an array into a single value.
863 The operand is available as :data:`Operand`.
865 .. admonition:: Example
867 .. code-block:: VHDL
869 res := nor operand;
870 -- ^^^^^^^^^^^ <- the expression
871 -- ^^^^^^^ <- Operand
872 """
873 _FORMAT: ClassVar[Tuple[str, str]] = ("nor ", "")
876@export
877class UnaryXorExpression(UnaryExpression):
878 """
879 Represents a ``xor`` reduction expression.
881 A reduction operator folds all elements of an array into a single value.
882 The operand is available as :data:`Operand`.
884 .. admonition:: Example
886 .. code-block:: VHDL
888 res := xor operand;
889 -- ^^^^^^^^^^^ <- the expression
890 -- ^^^^^^^ <- Operand
891 """
892 _FORMAT: ClassVar[Tuple[str, str]] = ("xor ", "")
895@export
896class UnaryXnorExpression(UnaryExpression):
897 """
898 Represents a ``xnor`` reduction expression.
900 A reduction operator folds all elements of an array into a single value.
901 The operand is available as :data:`Operand`.
903 .. admonition:: Example
905 .. code-block:: VHDL
907 res := xnor operand;
908 -- ^^^^^^^^^^^^ <- the expression
909 -- ^^^^^^^ <- Operand
910 """
911 _FORMAT: ClassVar[Tuple[str, str]] = ("xnor ", "")
914@export
915class AbsoluteExpression(UnaryExpression):
916 """
917 Represents an absolute value expression (``abs``).
919 The operand is available as :data:`Operand`.
921 .. admonition:: Example
923 .. code-block:: VHDL
925 res := abs operand;
926 -- ^^^^^^^^^^^ <- the expression
927 -- ^^^^^^^ <- Operand
928 """
929 _FORMAT: ClassVar[Tuple[str, str]] = ("abs ", "")
932@export
933class TypeConversion(UnaryExpression):
934 """
935 Represents a type conversion.
937 A type conversion converts its operand (:data:`Operand`) to the target subtype
938 (:data:`TargetSubtype`). Unlike every other :class:`UnaryExpression`, its "operator" is the target
939 type name itself rather than a fixed string, so it carries its own subtype and renders itself.
941 .. admonition:: Example
943 .. code-block:: VHDL
945 res := integer(val);
946 -- ^^^^^^^ <- TargetSubtype
947 -- ^^^ <- Operand
948 """
950 _targetSubtype: SubtypeSymbol #: Reference to the subtype the expression is converted to.
952 def __init__(self, targetSubtype: SubtypeSymbol, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
953 """
954 Initializes a type conversion.
956 :param targetSubtype: Reference to the subtype the expression is converted to.
957 :param operand: The expression the operator is applied to.
958 :param parent: The parent model entity of this entity.
959 """
960 super().__init__(operand, parent)
962 self._targetSubtype = targetSubtype
963 targetSubtype.Parent = self
965 @readonly
966 def TargetSubtype(self) -> SubtypeSymbol:
967 """
968 Read-only property to access the target subtype (:attr:`_targetSubtype`).
970 :returns: The target subtype.
971 """
972 return self._targetSubtype
974 def __str__(self) -> str:
975 """
976 Formats the type conversion.
978 **Format:** ``integer(val)``
980 :returns: Formatted type conversion.
981 """
982 return f"{self._targetSubtype!s}({self._operand!s})"
985@export
986class SubExpression(UnaryExpression, ParenthesisExpression):
987 """
988 Represents a parenthesized sub-expression.
990 The operand is available as :data:`Operand`.
992 .. admonition:: Example
994 .. code-block:: VHDL
996 res := (lhs + rhs);
997 -- ^^^^^^^^^^^ <- the sub-expression
998 -- ^^^^^^^^^ <- Operand
999 """
1000 _FORMAT: ClassVar[Tuple[str, str]] = ("(", ")")
1003@export
1004class BinaryExpression(BaseExpression):
1005 """
1006 Represents the base-class of all binary expressions.
1008 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1010 .. seealso::
1012 * :class:`Range expression <pyVHDLModel.Expression.RangeExpression>`
1013 * :class:`Adding expression <pyVHDLModel.Expression.AddingExpression>`
1014 * :class:`Multiplying expression <pyVHDLModel.Expression.MultiplyingExpression>`
1015 * :class:`Logical expression <pyVHDLModel.Expression.LogicalExpression>`
1016 * :class:`Relational expression <pyVHDLModel.Expression.RelationalExpression>`
1017 * :class:`Shift expression <pyVHDLModel.Expression.ShiftExpression>`
1018 """
1020 _FORMAT: ClassVar[Tuple[str, str, str]] #: The operator's string representation as (prefix, infix, suffix).
1021 _leftOperand: ExpressionUnion #: The expression left of the operator.
1022 _rightOperand: ExpressionUnion #: The expression right of the operator.
1024 def __init__(self, leftOperand: ExpressionUnion, rightOperand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
1025 """
1026 Initializes a binary expression.
1028 :param leftOperand: The expression left of the operator.
1029 :param rightOperand: The expression right of the operator.
1030 :param parent: The parent model entity of this entity.
1031 """
1032 super().__init__(parent)
1034 self._leftOperand = leftOperand
1035 leftOperand.Parent = self
1037 self._rightOperand = rightOperand
1038 rightOperand.Parent = self
1040 @readonly
1041 def LeftOperand(self) -> ExpressionUnion:
1042 """
1043 Read-only property to access the left operand (:attr:`_leftOperand`).
1045 :returns: The left operand.
1046 """
1047 return self._leftOperand
1049 @readonly
1050 def RightOperand(self) -> ExpressionUnion:
1051 """
1052 Read-only property to access the right operand (:attr:`_rightOperand`).
1054 :returns: The right operand.
1055 """
1056 return self._rightOperand
1058 def __str__(self) -> str:
1059 """
1060 Formats the binary expression.
1062 **Format:** ``lhs + rhs``
1064 :returns: Formatted binary expression.
1065 """
1066 return "{leftOperator}{leftOperand!s}{middleOperator}{rightOperand!s}{rightOperator}".format(
1067 leftOperator=self._FORMAT[0],
1068 leftOperand=self._leftOperand,
1069 middleOperator=self._FORMAT[1],
1070 rightOperand=self._rightOperand,
1071 rightOperator=self._FORMAT[2],
1072 )
1075@export
1076class RangeExpression(BinaryExpression):
1077 """
1078 Represents the base-class of range expressions.
1080 A range has a direction (:data:`Direction`) and two bounds. Both operands are available as :data:`LeftOperand` and
1081 :data:`RightOperand`.
1083 .. seealso::
1085 * :class:`Ascending range expression <pyVHDLModel.Expression.AscendingRangeExpression>`
1086 * :class:`Descending range expression <pyVHDLModel.Expression.DescendingRangeExpression>`
1087 """
1088 _direction: ClassVar[Direction] #: The range's direction, either ascending (``to``) or descending (``downto``).
1090 @readonly
1091 def Direction(self) -> Direction:
1092 """
1093 Read-only property to access the direction (:attr:`_direction`).
1095 :returns: The direction.
1096 """
1097 return self._direction
1100@export
1101class AscendingRangeExpression(RangeExpression):
1102 """
1103 Represents an ascending range expression (``to``).
1105 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1107 .. admonition:: Example
1109 .. code-block:: VHDL
1111 res := v(0 to 3);
1112 -- ^^^^^^ <- the range
1113 -- ^ <- LeftOperand
1114 -- ^ <- RightOperand
1115 """
1116 _direction: ClassVar[Direction] = Direction.To
1117 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " to ", "")
1120@export
1121class DescendingRangeExpression(RangeExpression):
1122 """
1123 Represents a descending range expression (``downto``).
1125 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1127 .. admonition:: Example
1129 .. code-block:: VHDL
1131 res := v(7 downto 4);
1132 -- ^^^^^^^^^^ <- the range
1133 -- ^ <- LeftOperand
1134 -- ^ <- RightOperand
1135 """
1136 _direction: ClassVar[Direction] = Direction.DownTo
1137 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " downto ", "")
1140@export
1141class AddingExpression(BinaryExpression):
1142 """
1143 Represents the base-class of all adding expressions: ``+``, ``-`` and ``&``.
1145 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1147 .. seealso::
1149 * :class:`Addition expression <pyVHDLModel.Expression.AdditionExpression>`
1150 * :class:`Subtraction expression <pyVHDLModel.Expression.SubtractionExpression>`
1151 * :class:`Concatenation expression <pyVHDLModel.Expression.ConcatenationExpression>`
1152 """
1155@export
1156class AdditionExpression(AddingExpression):
1157 """
1158 Represents an addition expression (``+``).
1160 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1162 .. admonition:: Example
1164 .. code-block:: VHDL
1166 res := lhs + rhs;
1167 -- ^^^^^^^^^ <- the expression
1168 -- ^^^ <- LeftOperand
1169 -- ^^^ <- RightOperand
1170 """
1171 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " + ", "")
1174@export
1175class SubtractionExpression(AddingExpression):
1176 """
1177 Represents a subtraction expression (``-``).
1179 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1181 .. admonition:: Example
1183 .. code-block:: VHDL
1185 res := lhs - rhs;
1186 -- ^^^^^^^^^ <- the expression
1187 -- ^^^ <- LeftOperand
1188 -- ^^^ <- RightOperand
1189 """
1190 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " - ", "")
1193@export
1194class ConcatenationExpression(AddingExpression):
1195 """
1196 Represents a concatenation expression (``&``).
1198 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1200 .. admonition:: Example
1202 .. code-block:: VHDL
1204 res := lhs & rhs;
1205 -- ^^^^^^^^^ <- the expression
1206 -- ^^^ <- LeftOperand
1207 -- ^^^ <- RightOperand
1208 """
1209 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " & ", "")
1212@export
1213class MultiplyingExpression(BinaryExpression):
1214 """
1215 Represents the base-class of all multiplying expressions: ``*``, ``/``, ``rem``, ``mod`` and ``**``.
1217 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1219 .. seealso::
1221 * :class:`Multiply expression <pyVHDLModel.Expression.MultiplyExpression>`
1222 * :class:`Division expression <pyVHDLModel.Expression.DivisionExpression>`
1223 * :class:`Remainder expression <pyVHDLModel.Expression.RemainderExpression>`
1224 * :class:`Modulo expression <pyVHDLModel.Expression.ModuloExpression>`
1225 * :class:`Exponentiation expression <pyVHDLModel.Expression.ExponentiationExpression>`
1226 """
1229@export
1230class MultiplyExpression(MultiplyingExpression):
1231 """
1232 Represents a multiplication expression (``*``).
1234 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1236 .. admonition:: Example
1238 .. code-block:: VHDL
1240 res := lhs * rhs;
1241 -- ^^^^^^^^^ <- the expression
1242 -- ^^^ <- LeftOperand
1243 -- ^^^ <- RightOperand
1244 """
1245 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " * ", "")
1248@export
1249class DivisionExpression(MultiplyingExpression):
1250 """
1251 Represents a division expression (``/``).
1253 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1255 .. admonition:: Example
1257 .. code-block:: VHDL
1259 res := lhs / rhs;
1260 -- ^^^^^^^^^ <- the expression
1261 -- ^^^ <- LeftOperand
1262 -- ^^^ <- RightOperand
1263 """
1264 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " / ", "")
1267@export
1268class RemainderExpression(MultiplyingExpression):
1269 """
1270 Represents a remainder expression (``rem``).
1272 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1274 .. admonition:: Example
1276 .. code-block:: VHDL
1278 res := lhs rem rhs;
1279 -- ^^^^^^^^^^^ <- the expression
1280 -- ^^^ <- LeftOperand
1281 -- ^^^ <- RightOperand
1282 """
1283 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " rem ", "")
1286@export
1287class ModuloExpression(MultiplyingExpression):
1288 """
1289 Represents a modulo expression (``mod``).
1291 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1293 .. admonition:: Example
1295 .. code-block:: VHDL
1297 res := lhs mod rhs;
1298 -- ^^^^^^^^^^^ <- the expression
1299 -- ^^^ <- LeftOperand
1300 -- ^^^ <- RightOperand
1301 """
1302 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " mod ", "")
1305@export
1306class ExponentiationExpression(MultiplyingExpression):
1307 """
1308 Represents an exponentiation expression (``**``).
1310 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1312 .. admonition:: Example
1314 .. code-block:: VHDL
1316 res := lhs ** rhs;
1317 -- ^^^^^^^^^^ <- the expression
1318 -- ^^^ <- LeftOperand
1319 -- ^^^ <- RightOperand
1320 """
1321 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", "**", "")
1324@export
1325class LogicalExpression(BinaryExpression):
1326 """
1327 Represents the base-class of all binary logical expressions.
1329 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1331 .. seealso::
1333 * :class:`And expression <pyVHDLModel.Expression.AndExpression>`
1334 * :class:`Nand expression <pyVHDLModel.Expression.NandExpression>`
1335 * :class:`Or expression <pyVHDLModel.Expression.OrExpression>`
1336 * :class:`Nor expression <pyVHDLModel.Expression.NorExpression>`
1337 * :class:`Xor expression <pyVHDLModel.Expression.XorExpression>`
1338 * :class:`Xnor expression <pyVHDLModel.Expression.XnorExpression>`
1339 """
1342@export
1343class AndExpression(LogicalExpression):
1344 """
1345 Represents a logical ``and`` expression.
1347 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1349 .. admonition:: Example
1351 .. code-block:: VHDL
1353 res := lhs and rhs;
1354 -- ^^^^^^^^^^^ <- the expression
1355 -- ^^^ <- LeftOperand
1356 -- ^^^ <- RightOperand
1357 """
1358 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " and ", "")
1361@export
1362class NandExpression(LogicalExpression):
1363 """
1364 Represents a logical ``nand`` expression.
1366 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1368 .. admonition:: Example
1370 .. code-block:: VHDL
1372 res := lhs nand rhs;
1373 -- ^^^^^^^^^^^^ <- the expression
1374 -- ^^^ <- LeftOperand
1375 -- ^^^ <- RightOperand
1376 """
1377 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " nand ", "")
1380@export
1381class OrExpression(LogicalExpression):
1382 """
1383 Represents a logical ``or`` expression.
1385 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1387 .. admonition:: Example
1389 .. code-block:: VHDL
1391 res := lhs or rhs;
1392 -- ^^^^^^^^^^ <- the expression
1393 -- ^^^ <- LeftOperand
1394 -- ^^^ <- RightOperand
1395 """
1396 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " or ", "")
1399@export
1400class NorExpression(LogicalExpression):
1401 """
1402 Represents a logical ``nor`` expression.
1404 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1406 .. admonition:: Example
1408 .. code-block:: VHDL
1410 res := lhs nor rhs;
1411 -- ^^^^^^^^^^^ <- the expression
1412 -- ^^^ <- LeftOperand
1413 -- ^^^ <- RightOperand
1414 """
1415 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " nor ", "")
1418@export
1419class XorExpression(LogicalExpression):
1420 """
1421 Represents a logical ``xor`` expression.
1423 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1425 .. admonition:: Example
1427 .. code-block:: VHDL
1429 res := lhs xor rhs;
1430 -- ^^^^^^^^^^^ <- the expression
1431 -- ^^^ <- LeftOperand
1432 -- ^^^ <- RightOperand
1433 """
1434 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " xor ", "")
1437@export
1438class XnorExpression(LogicalExpression):
1439 """
1440 Represents a logical ``xnor`` expression.
1442 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1444 .. admonition:: Example
1446 .. code-block:: VHDL
1448 res := lhs xnor rhs;
1449 -- ^^^^^^^^^^^^ <- the expression
1450 -- ^^^ <- LeftOperand
1451 -- ^^^ <- RightOperand
1452 """
1453 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " xnor ", "")
1456@export
1457class RelationalExpression(BinaryExpression):
1458 """
1459 Represents the base-class of all relational expressions.
1461 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1463 .. seealso::
1465 * :class:`Equal expression <pyVHDLModel.Expression.EqualExpression>`
1466 * :class:`Unequal expression <pyVHDLModel.Expression.UnequalExpression>`
1467 * :class:`Greater than expression <pyVHDLModel.Expression.GreaterThanExpression>`
1468 * :class:`Greater equal expression <pyVHDLModel.Expression.GreaterEqualExpression>`
1469 * :class:`Less than expression <pyVHDLModel.Expression.LessThanExpression>`
1470 * :class:`Less equal expression <pyVHDLModel.Expression.LessEqualExpression>`
1471 * :class:`Matching relational expression <pyVHDLModel.Expression.MatchingRelationalExpression>`
1472 """
1475@export
1476class EqualExpression(RelationalExpression):
1477 """
1478 Represents an equality expression (``=``).
1480 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1482 .. admonition:: Example
1484 .. code-block:: VHDL
1486 res := lhs = rhs;
1487 -- ^^^^^^^^^ <- the expression
1488 -- ^^^ <- LeftOperand
1489 -- ^^^ <- RightOperand
1490 """
1491 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " = ", "")
1494@export
1495class UnequalExpression(RelationalExpression):
1496 """
1497 Represents an inequality expression (``/=``).
1499 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1501 .. admonition:: Example
1503 .. code-block:: VHDL
1505 res := lhs /= rhs;
1506 -- ^^^^^^^^^^ <- the expression
1507 -- ^^^ <- LeftOperand
1508 -- ^^^ <- RightOperand
1509 """
1510 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " /= ", "")
1513@export
1514class GreaterThanExpression(RelationalExpression):
1515 """
1516 Represents a greater-than expression (``>``).
1518 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1520 .. admonition:: Example
1522 .. code-block:: VHDL
1524 res := lhs > rhs;
1525 -- ^^^^^^^^^ <- the expression
1526 -- ^^^ <- LeftOperand
1527 -- ^^^ <- RightOperand
1528 """
1529 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " > ", "")
1532@export
1533class GreaterEqualExpression(RelationalExpression):
1534 """
1535 Represents a greater-or-equal expression (``>=``).
1537 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1539 .. admonition:: Example
1541 .. code-block:: VHDL
1543 res := lhs >= rhs;
1544 -- ^^^^^^^^^^ <- the expression
1545 -- ^^^ <- LeftOperand
1546 -- ^^^ <- RightOperand
1547 """
1548 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " >= ", "")
1551@export
1552class LessThanExpression(RelationalExpression):
1553 """
1554 Represents a less-than expression (``<``).
1556 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1558 .. admonition:: Example
1560 .. code-block:: VHDL
1562 res := lhs < rhs;
1563 -- ^^^^^^^^^ <- the expression
1564 -- ^^^ <- LeftOperand
1565 -- ^^^ <- RightOperand
1566 """
1567 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " < ", "")
1570@export
1571class LessEqualExpression(RelationalExpression):
1572 """
1573 Represents a less-or-equal expression (``<=``).
1575 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1577 .. admonition:: Example
1579 .. code-block:: VHDL
1581 res := lhs <= rhs;
1582 -- ^^^^^^^^^^ <- the expression
1583 -- ^^^ <- LeftOperand
1584 -- ^^^ <- RightOperand
1585 """
1586 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " <= ", "")
1589@export
1590class MatchingRelationalExpression(RelationalExpression):
1591 """
1592 Represents the base-class of all matching relational expressions.
1594 Matching operators return a ``bit``/``std_ulogic`` rather than a ``boolean``. Both operands are available as
1595 :data:`LeftOperand` and :data:`RightOperand`.
1597 .. seealso::
1599 * :class:`Matching equal expression <pyVHDLModel.Expression.MatchingEqualExpression>`
1600 * :class:`Matching unequal expression <pyVHDLModel.Expression.MatchingUnequalExpression>`
1601 * :class:`Matching greater than expression <pyVHDLModel.Expression.MatchingGreaterThanExpression>`
1602 * :class:`Matching greater equal expression <pyVHDLModel.Expression.MatchingGreaterEqualExpression>`
1603 * :class:`Matching less than expression <pyVHDLModel.Expression.MatchingLessThanExpression>`
1604 * :class:`Matching less equal expression <pyVHDLModel.Expression.MatchingLessEqualExpression>`
1605 """
1606 pass
1609@export
1610class MatchingEqualExpression(MatchingRelationalExpression):
1611 """
1612 Represents a matching equality expression (``?=``).
1614 Unlike ``=``, a matching operator returns a ``bit``/``std_ulogic``.
1615 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1617 .. admonition:: Example
1619 .. code-block:: VHDL
1621 res := lhs ?= rhs;
1622 -- ^^^^^^^^^^ <- the expression
1623 -- ^^^ <- LeftOperand
1624 -- ^^^ <- RightOperand
1625 """
1626 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?= ", "")
1629@export
1630class MatchingUnequalExpression(MatchingRelationalExpression):
1631 """
1632 Represents a matching inequality expression (``?/=``).
1634 Unlike ``/=``, a matching operator returns a ``bit``/``std_ulogic``.
1635 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1637 .. admonition:: Example
1639 .. code-block:: VHDL
1641 res := lhs ?/= rhs;
1642 -- ^^^^^^^^^^^ <- the expression
1643 -- ^^^ <- LeftOperand
1644 -- ^^^ <- RightOperand
1645 """
1646 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?/= ", "")
1649@export
1650class MatchingGreaterThanExpression(MatchingRelationalExpression):
1651 """
1652 Represents a matching greater-than expression (``?>``).
1654 Unlike ``>``, a matching operator returns a ``bit``/``std_ulogic``.
1655 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1657 .. admonition:: Example
1659 .. code-block:: VHDL
1661 res := lhs ?> rhs;
1662 -- ^^^^^^^^^^ <- the expression
1663 -- ^^^ <- LeftOperand
1664 -- ^^^ <- RightOperand
1665 """
1666 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?> ", "")
1669@export
1670class MatchingGreaterEqualExpression(MatchingRelationalExpression):
1671 """
1672 Represents a matching greater-or-equal expression (``?>=``).
1674 Unlike ``>=``, a matching operator returns a ``bit``/``std_ulogic``.
1675 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1677 .. admonition:: Example
1679 .. code-block:: VHDL
1681 res := lhs ?>= rhs;
1682 -- ^^^^^^^^^^^ <- the expression
1683 -- ^^^ <- LeftOperand
1684 -- ^^^ <- RightOperand
1685 """
1686 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?>= ", "")
1689@export
1690class MatchingLessThanExpression(MatchingRelationalExpression):
1691 """
1692 Represents a matching less-than expression (``?<``).
1694 Unlike ``<``, a matching operator returns a ``bit``/``std_ulogic``.
1695 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1697 .. admonition:: Example
1699 .. code-block:: VHDL
1701 res := lhs ?< rhs;
1702 -- ^^^^^^^^^^ <- the expression
1703 -- ^^^ <- LeftOperand
1704 -- ^^^ <- RightOperand
1705 """
1706 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?< ", "")
1709@export
1710class MatchingLessEqualExpression(MatchingRelationalExpression):
1711 """
1712 Represents a matching less-or-equal expression (``?<=``).
1714 Unlike ``<=``, a matching operator returns a ``bit``/``std_ulogic``.
1715 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1717 .. admonition:: Example
1719 .. code-block:: VHDL
1721 res := lhs ?<= rhs;
1722 -- ^^^^^^^^^^^ <- the expression
1723 -- ^^^ <- LeftOperand
1724 -- ^^^ <- RightOperand
1725 """
1726 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ?<= ", "")
1729@export
1730class ShiftExpression(BinaryExpression):
1731 """
1732 Represents the base-class of all shift and rotate expressions.
1734 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1736 .. seealso::
1738 * :class:`Shift logic expression <pyVHDLModel.Expression.ShiftLogicExpression>`
1739 * :class:`Shift arithmetic expression <pyVHDLModel.Expression.ShiftArithmeticExpression>`
1740 * :class:`Rotate expression <pyVHDLModel.Expression.RotateExpression>`
1741 """
1744@export
1745class ShiftLogicExpression(ShiftExpression):
1746 """
1747 Represents the base-class of the logical shift expressions ``srl`` and ``sll``.
1749 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1751 .. seealso::
1753 * :class:`Shift right logic expression <pyVHDLModel.Expression.ShiftRightLogicExpression>`
1754 * :class:`Shift left logic expression <pyVHDLModel.Expression.ShiftLeftLogicExpression>`
1755 """
1756 pass
1759@export
1760class ShiftArithmeticExpression(ShiftExpression):
1761 """
1762 Represents the base-class of the arithmetic shift expressions ``sra`` and ``sla``.
1764 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1766 .. seealso::
1768 * :class:`Shift right arithmetic expression <pyVHDLModel.Expression.ShiftRightArithmeticExpression>`
1769 * :class:`Shift left arithmetic expression <pyVHDLModel.Expression.ShiftLeftArithmeticExpression>`
1770 """
1771 pass
1774@export
1775class RotateExpression(ShiftExpression):
1776 """
1777 Represents the base-class of the rotate expressions ``ror`` and ``rol``.
1779 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1781 .. seealso::
1783 * :class:`Rotate right expression <pyVHDLModel.Expression.RotateRightExpression>`
1784 * :class:`Rotate left expression <pyVHDLModel.Expression.RotateLeftExpression>`
1785 """
1786 pass
1789@export
1790class ShiftRightLogicExpression(ShiftLogicExpression):
1791 """
1792 Represents a logical right shift expression (``srl``).
1794 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1796 .. admonition:: Example
1798 .. code-block:: VHDL
1800 res := lhs srl rhs;
1801 -- ^^^^^^^^^^^ <- the expression
1802 -- ^^^ <- LeftOperand
1803 -- ^^^ <- RightOperand
1804 """
1805 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " srl ", "")
1808@export
1809class ShiftLeftLogicExpression(ShiftLogicExpression):
1810 """
1811 Represents a logical left shift expression (``sll``).
1813 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1815 .. admonition:: Example
1817 .. code-block:: VHDL
1819 res := lhs sll rhs;
1820 -- ^^^^^^^^^^^ <- the expression
1821 -- ^^^ <- LeftOperand
1822 -- ^^^ <- RightOperand
1823 """
1824 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " sll ", "")
1827@export
1828class ShiftRightArithmeticExpression(ShiftArithmeticExpression):
1829 """
1830 Represents an arithmetic right shift expression (``sra``).
1832 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1834 .. admonition:: Example
1836 .. code-block:: VHDL
1838 res := lhs sra rhs;
1839 -- ^^^^^^^^^^^ <- the expression
1840 -- ^^^ <- LeftOperand
1841 -- ^^^ <- RightOperand
1842 """
1843 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " sra ", "")
1846@export
1847class ShiftLeftArithmeticExpression(ShiftArithmeticExpression):
1848 """
1849 Represents an arithmetic left shift expression (``sla``).
1851 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1853 .. admonition:: Example
1855 .. code-block:: VHDL
1857 res := lhs sla rhs;
1858 -- ^^^^^^^^^^^ <- the expression
1859 -- ^^^ <- LeftOperand
1860 -- ^^^ <- RightOperand
1861 """
1862 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " sla ", "")
1865@export
1866class RotateRightExpression(RotateExpression):
1867 """
1868 Represents a right rotate expression (``ror``).
1870 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1872 .. admonition:: Example
1874 .. code-block:: VHDL
1876 res := lhs ror rhs;
1877 -- ^^^^^^^^^^^ <- the expression
1878 -- ^^^ <- LeftOperand
1879 -- ^^^ <- RightOperand
1880 """
1881 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " ror ", "")
1884@export
1885class RotateLeftExpression(RotateExpression):
1886 """
1887 Represents a left rotate expression (``rol``).
1889 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1891 .. admonition:: Example
1893 .. code-block:: VHDL
1895 res := lhs rol rhs;
1896 -- ^^^^^^^^^^^ <- the expression
1897 -- ^^^ <- LeftOperand
1898 -- ^^^ <- RightOperand
1899 """
1900 _FORMAT: ClassVar[Tuple[str, str, str]] = ("", " rol ", "")
1903@export
1904class QualifiedExpression(BaseExpression, ParenthesisExpression):
1905 """
1906 Represents a qualified expression.
1908 A qualified expression states the subtype (:data:`Subtype`) of its operand (:data:`Operand`),
1909 resolving which of several overloaded meanings is intended.
1911 .. admonition:: Example
1913 .. code-block:: VHDL
1915 res := byte'(others => '0');
1916 -- ^^^^ <- Subtype
1917 -- ^^^^^^^^^^^^^^^ <- Operand
1918 """
1919 _operand: ExpressionUnion #: The expression being qualified.
1920 _subtype: Symbol #: Reference to the subtype qualifying the expression.
1922 def __init__(self, subtype: Symbol, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
1923 """
1924 Initializes a qualified expression.
1926 :param subtype: Reference to the subtype qualifying the expression.
1927 :param operand: The expression being qualified.
1928 :param parent: The parent model entity of this entity.
1929 """
1930 super().__init__(parent)
1932 self._operand = operand
1933 operand.Parent = self
1935 self._subtype = subtype
1936 subtype.Parent = self
1938 @readonly
1939 def Operand(self) -> ExpressionUnion:
1940 """
1941 Read-only property to access the operand (:attr:`_operand`).
1943 :returns: The operand.
1944 """
1945 return self._operand
1947 @readonly
1948 def Subtype(self) -> Symbol:
1949 """
1950 Read-only property to access the subtype (:attr:`_subtype`).
1952 :returns: The subtype.
1953 """
1954 return self._subtype
1956 def __str__(self) -> str:
1957 """
1958 Formats the qualified expression.
1960 **Format:** ``byte'(val)``
1962 :returns: Formatted qualified expression.
1963 """
1964 return f"{self._subtype}'({self._operand!s})"
1967@export
1968class TernaryExpression(BaseExpression):
1969 """
1970 Represents the base-class of all ternary expressions.
1972 .. seealso::
1974 * :class:`When else expression <pyVHDLModel.Expression.WhenElseExpression>`
1975 """
1977 _FORMAT: ClassVar[Tuple[str, str, str, str]] #: The operator's string representation as four fragments.
1978 _firstOperand: ExpressionUnion #: The operator's first operand.
1979 _secondOperand: ExpressionUnion #: The operator's second operand.
1980 _thirdOperand: ExpressionUnion #: The operator's third operand.
1982 def __init__(
1983 self,
1984 firstOperand: ExpressionUnion,
1985 secondOperand: ExpressionUnion,
1986 thirdOperand: ExpressionUnion,
1987 parent: Nullable[ModelEntity] = None
1988 ) -> None:
1989 """
1990 Initializes a ternary expression.
1992 :param firstOperand: The operator's first operand.
1993 :param secondOperand: The operator's second operand.
1994 :param thirdOperand: The operator's third operand.
1995 :param parent: The parent model entity of this entity.
1996 """
1997 super().__init__(parent)
1999 self._firstOperand = firstOperand
2000 firstOperand.Parent = self
2002 self._secondOperand = secondOperand
2003 secondOperand.Parent = self
2005 self._thirdOperand = thirdOperand
2006 thirdOperand.Parent = self
2008 def __str__(self) -> str:
2009 """
2010 Formats the ternary expression.
2012 **Format:** ``val when cond else other``
2014 :returns: Formatted ternary expression.
2015 """
2016 return "{beforeFirstOperator}{firstOperand!s}{beforeSecondOperator}{secondOperand!s}{beforeThirdOperator}{thirdOperand!s}{lastOperator}".format(
2017 beforeFirstOperator=self._FORMAT[0],
2018 firstOperand=self._firstOperand,
2019 beforeSecondOperator=self._FORMAT[1],
2020 secondOperand=self._secondOperand,
2021 beforeThirdOperator=self._FORMAT[2],
2022 thirdOperand=self._thirdOperand,
2023 lastOperator=self._FORMAT[3],
2024 )
2027@export
2028class WhenElseExpression(TernaryExpression):
2029 """
2030 Represents a conditional expression.
2032 A conditional expression selects between two values (:data:`ThenValue`, :data:`ElseValue`) based on
2033 a condition (:data:`Condition`). It is usable anywhere an expression is expected - distinct from
2034 :class:`~pyVHDLModel.Common.ConditionalExpression`, which models the cascading ``when``/``else``
2035 list of a conditional *assignment*.
2037 .. admonition:: Example
2039 .. code-block:: VHDL
2041 res := a when f else b;
2042 -- ^ <- ThenValue
2043 -- ^ <- Condition
2044 -- ^ <- ElseValue
2045 """
2047 _FORMAT: ClassVar[Tuple[str, str, str, str]] = ("", " when ", " else ", "")
2049 def __init__(
2050 self,
2051 thenValue: ExpressionUnion,
2052 condition: ExpressionUnion,
2053 elseValue: ExpressionUnion,
2054 parent: Nullable[ModelEntity] = None
2055 ) -> None:
2056 """
2057 Initializes a conditional expression.
2059 :param thenValue: The value if the condition holds.
2060 :param condition: The condition selecting between both values.
2061 :param elseValue: The value if the condition does not hold.
2062 :param parent: The parent model entity of this entity.
2063 """
2064 super().__init__(thenValue, condition, elseValue, parent)
2066 @readonly
2067 def ThenValue(self) -> ExpressionUnion:
2068 """
2069 Read-only property to access the then value (:attr:`_firstOperand`).
2071 :returns: The then value.
2072 """
2073 return self._firstOperand
2075 @readonly
2076 def Condition(self) -> ExpressionUnion:
2077 """
2078 Read-only property to access the condition (:attr:`_secondOperand`).
2080 :returns: The condition.
2081 """
2082 return self._secondOperand
2084 @readonly
2085 def ElseValue(self) -> ExpressionUnion:
2086 """
2087 Read-only property to access the else value (:attr:`_thirdOperand`).
2089 :returns: The else value.
2090 """
2091 return self._thirdOperand
2094@export
2095class FunctionCall(BaseExpression):
2096 """
2097 Represents a call to a function.
2099 .. admonition:: Example
2101 .. code-block:: VHDL
2103 res := maximum(a, b);
2104 -- ^^^^^^^^^^^^^ <- the call
2105 """
2106 pass
2109@export
2110class Allocation(BaseExpression):
2111 """
2112 Represents the base-class of all allocations via ``new``.
2114 .. seealso::
2116 * :class:`Subtype allocation <pyVHDLModel.Expression.SubtypeAllocation>`
2117 * :class:`Qualified expression allocation <pyVHDLModel.Expression.QualifiedExpressionAllocation>`
2118 """
2119 pass
2122@export
2123class SubtypeAllocation(Allocation):
2124 """
2125 Represents an allocation of a subtype via ``new``.
2127 The allocated subtype is available as :data:`Subtype`. The allocated object is default-initialized.
2129 .. admonition:: Example
2131 .. code-block:: VHDL
2133 p := new integer;
2134 -- ^^^^^^^ <- Subtype
2135 """
2136 _subtype: Symbol #: Reference to the subtype being allocated.
2138 def __init__(self, subtype: Symbol, parent: Nullable[ModelEntity] = None) -> None:
2139 """
2140 Initializes an allocation of a subtype via ``new``.
2142 :param subtype: Reference to the subtype being allocated.
2143 :param parent: The parent model entity of this entity.
2144 """
2145 super().__init__(parent)
2147 self._subtype = subtype
2148 subtype.Parent = self
2150 @readonly
2151 def Subtype(self) -> Symbol:
2152 """
2153 Read-only property to access the subtype (:attr:`_subtype`).
2155 :returns: The subtype.
2156 """
2157 return self._subtype
2159 def __str__(self) -> str:
2160 """
2161 Formats the subtype allocation.
2163 **Format:** ``new node``
2165 :returns: Formatted subtype allocation.
2166 """
2167 return f"new {self._subtype!s}"
2170@export
2171class QualifiedExpressionAllocation(Allocation):
2172 """
2173 Represents an allocation initialized by a qualified expression.
2175 The qualified expression providing the initial value is available as :data:`QualifiedExpression`.
2177 .. admonition:: Example
2179 .. code-block:: VHDL
2181 p := new integer'(5);
2182 -- ^^^^^^^^^^^ <- QualifiedExpression
2183 """
2184 _qualifiedExpression: QualifiedExpression #: The qualified expression the allocated object is initialized with.
2186 def __init__(self, qualifiedExpression: QualifiedExpression, parent: Nullable[ModelEntity] = None) -> None:
2187 """
2188 Initializes an allocation initialized by a qualified expression.
2190 :param qualifiedExpression: The qualified expression the allocated object is initialized with.
2191 :param parent: The parent model entity of this entity.
2192 """
2193 super().__init__(parent)
2195 self._qualifiedExpression = qualifiedExpression
2196 qualifiedExpression.Parent = self
2198 @readonly
2199 def QualifiedExpression(self) -> QualifiedExpression:
2200 """
2201 Read-only property to access the qualified expression (:attr:`_qualifiedExpression`).
2203 :returns: The qualified expression.
2204 """
2205 return self._qualifiedExpression
2207 def __str__(self) -> str:
2208 """
2209 Formats the qualified expression allocation.
2211 **Format:** ``new byte'(val)``
2213 :returns: Formatted qualified expression allocation.
2214 """
2215 return f"new {self._qualifiedExpression!s}"
2218@export
2219class AggregateElement(ModelEntity):
2220 """
2221 Represents the base-class of all aggregate elements.
2223 Every element carries the value assigned to it (:data:`Expression`).
2225 .. seealso::
2227 * :class:`Simple aggregate element <pyVHDLModel.Expression.SimpleAggregateElement>`
2228 * :class:`Indexed aggregate element <pyVHDLModel.Expression.IndexedAggregateElement>`
2229 * :class:`Ranged aggregate element <pyVHDLModel.Expression.RangedAggregateElement>`
2230 * :class:`Named aggregate element <pyVHDLModel.Expression.NamedAggregateElement>`
2231 * :class:`Others aggregate element <pyVHDLModel.Expression.OthersAggregateElement>`
2232 """
2234 _expression: ExpressionUnion #: The expression this aggregate element supplies.
2236 def __init__(self, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2237 """
2238 Initializes an aggregate element.
2240 :param expression: The expression this aggregate element supplies.
2241 :param parent: The parent model entity of this entity.
2242 """
2243 super().__init__(parent)
2245 self._expression = expression
2246 expression.Parent = self
2248 @readonly
2249 def Expression(self) -> ExpressionUnion:
2250 """
2251 Read-only property to access the expression (:attr:`_expression`).
2253 :returns: The expression.
2254 """
2255 return self._expression
2258@export
2259class SimpleAggregateElement(AggregateElement):
2260 """
2261 Represents an aggregate element given by position.
2263 A positional element has no choice of its own; only its value (:data:`Expression`).
2265 .. admonition:: Example
2267 .. code-block:: VHDL
2269 res := ('1', '0', '1', '0', '1', '0', '1', '0');
2270 -- ^^^ <- Expression
2271 """
2272 def __str__(self) -> str:
2273 """
2274 Formats the simple aggregate element.
2276 **Format:** ``val``
2278 :returns: Formatted simple aggregate element.
2279 """
2280 return str(self._expression)
2283@export
2284class IndexedAggregateElement(AggregateElement):
2285 """
2286 Represents an aggregate element chosen by an index.
2288 The index is available as :data:`Index`, the assigned value as :data:`Expression`.
2290 .. admonition:: Example
2292 .. code-block:: VHDL
2294 res := (0 => '1', others => '0');
2295 -- ^ <- Index
2296 -- ^^^ <- Expression
2297 """
2298 _index: int #: The index selecting the element this value is assigned to.
2300 def __init__(self, index: ExpressionUnion, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2301 """
2302 Initializes an aggregate element chosen by an index.
2304 :param index: The index selecting the element this value is assigned to.
2305 :param expression: The expression this aggregate element supplies.
2306 :param parent: The parent model entity of this entity.
2307 """
2308 super().__init__(expression, parent)
2310 self._index = index
2312 @readonly
2313 def Index(self) -> int:
2314 """
2315 Read-only property to access the index (:attr:`_index`).
2317 :returns: The index.
2318 """
2319 return self._index
2321 def __str__(self) -> str:
2322 """
2323 Formats the indexed aggregate element.
2325 **Format:** ``0 => val``
2327 :returns: Formatted indexed aggregate element.
2328 """
2329 return f"{self._index!s} => {self._expression!s}"
2332@export
2333class RangedAggregateElement(AggregateElement):
2334 """
2335 Represents an aggregate element chosen by a range.
2337 The range is available as :data:`Range`, the assigned value as :data:`Expression`.
2339 .. admonition:: Example
2341 .. code-block:: VHDL
2343 res := (1 to 3 => '0', others => '1');
2344 -- ^^^^^^ <- Range
2345 -- ^^^ <- Expression
2346 """
2347 _range: Range #: The range selecting the elements this value is assigned to.
2349 def __init__(self, rng: Range, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2350 """
2351 Initializes an aggregate element chosen by a range.
2353 :param rng: The range selecting the elements this value is assigned to.
2354 :param expression: The expression this aggregate element supplies.
2355 :param parent: The parent model entity of this entity.
2356 """
2357 super().__init__(expression, parent)
2359 self._range = rng
2360 rng.Parent = self
2362 @readonly
2363 def Range(self) -> Range:
2364 """
2365 Read-only property to access the range (:attr:`_range`).
2367 :returns: The range.
2368 """
2369 return self._range
2371 def __str__(self) -> str:
2372 """
2373 Formats the ranged aggregate element.
2375 **Format:** ``0 to 3 => val``
2377 :returns: Formatted ranged aggregate element.
2378 """
2379 return f"{self._range!s} => {self._expression!s}"
2382@export
2383class NamedAggregateElement(AggregateElement):
2384 """
2385 Represents an aggregate element chosen by a name.
2387 Used for record aggregates, where the choice names a record element (:data:`Name`).
2389 .. admonition:: Example
2391 .. code-block:: VHDL
2393 r := (a => '1', b => '0');
2394 -- ^ <- Name
2395 -- ^^^ <- Expression
2396 """
2397 _name: Symbol #: Reference to the name selecting the element this value is assigned to.
2399 def __init__(self, name: Symbol, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2400 """
2401 Initializes an aggregate element chosen by a name.
2403 :param name: Reference to the name selecting the element this value is assigned to.
2404 :param expression: The expression this aggregate element supplies.
2405 :param parent: The parent model entity of this entity.
2406 """
2407 super().__init__(expression, parent)
2409 self._name = name
2410 name.Parent = self
2412 @readonly
2413 def Name(self) -> Symbol:
2414 """
2415 Read-only property to access the name (:attr:`_name`).
2417 :returns: The name.
2418 """
2419 return self._name
2421 def __str__(self) -> str:
2422 """
2423 Formats the named aggregate element.
2425 **Format:** ``elem => val``
2427 :returns: Formatted named aggregate element.
2428 """
2429 return "{name!s} => {value!s}".format(
2430 name=self._name,
2431 value=self._expression,
2432 )
2435@export
2436class OthersAggregateElement(AggregateElement):
2437 """
2438 Represents the ``others`` element of an aggregate.
2440 It supplies the value (:data:`Expression`) for every choice not named explicitly.
2442 .. admonition:: Example
2444 .. code-block:: VHDL
2446 res := (0 => '1', others => '0');
2447 -- ^^^^^^ <- the choice
2448 -- ^^^ <- Expression
2449 """
2450 def __str__(self) -> str:
2451 """
2452 Formats the ``others`` aggregate element.
2454 **Format:** ``others => val``
2456 :returns: Formatted ``others`` aggregate element.
2457 """
2458 return "others => {value!s}".format(
2459 value=self._expression,
2460 )
2463@export
2464class Aggregate(BaseExpression):
2465 """
2466 Represents an aggregate.
2468 An aggregate composes a value from its elements (:data:`Elements`), each of which associates a
2469 choice with a value.
2471 .. admonition:: Example
2473 .. code-block:: VHDL
2475 res := (0 => '1', 1 to 3 => '0', others => '1');
2476 -- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ <- Elements
2477 """
2478 _elements: List[AggregateElement] #: List of all elements of this aggregate, in the order they were written.
2480 def __init__(self, elements: Iterable[AggregateElement], parent: Nullable[ModelEntity] = None) -> None:
2481 """
2482 Initializes an aggregate.
2484 :param elements: List of all elements of this aggregate, in the order they were written.
2485 :param parent: The parent model entity of this entity.
2486 """
2487 super().__init__(parent)
2489 self._elements = []
2490 for element in elements:
2491 self._elements.append(element)
2492 element.Parent = self
2494 @readonly
2495 def Elements(self) -> List[AggregateElement]:
2496 """
2497 Read-only property to access the elements (:attr:`_elements`).
2499 :returns: List of elements.
2500 """
2501 return self._elements
2503 def __str__(self) -> str:
2504 """
2505 Formats the aggregate.
2507 **Format:** ``(1, others => 0)``
2509 :returns: Formatted aggregate.
2510 """
2511 choices = [str(element) for element in self._elements]
2512 return "({choices})".format(
2513 choices=", ".join(choices)
2514 )