Coverage for pyVHDLModel/Expression.py: 99%
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8# ==================================================================================================================== #
9# Authors: #
10# Patrick Lehmann #
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13# ==================================================================================================================== #
14# Copyright 2017-2026 Patrick Lehmann - Boetzingen, Germany #
15# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany #
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17# Licensed under the Apache License, Version 2.0 (the "License"); #
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31#
32"""
33This module contains parts of an abstract document language model for VHDL.
35All declarations for literals, aggregates, operators forming an expressions.
36"""
37from __future__ import annotations
39from enum import Flag, IntEnum, unique
40from typing import TYPE_CHECKING, Iterable, Union, ClassVar, Optional as Nullable, Self
42from pyTooling.Common import getFullyQualifiedName
43from pyTooling.Decorators import export, readonly
44from pyTooling.MetaClasses import abstractclass
46from pyVHDLModel.Base import ModelEntity, Direction, Range, ReservedWord
47from pyVHDLModel.Exception import LiteralError
48from pyVHDLModel.Symbol import Symbol, SubtypeSymbol
49if TYPE_CHECKING: 49 ↛ 50line 49 didn't jump to line 50 because the condition on line 49 was never true
50 from pyVHDLModel.Visitor import Visitor
53ExpressionUnion = Union[
54 'BaseExpression',
55 'QualifiedExpression',
56 'FunctionCall',
57 'TypeConversion',
58 # ConstantOrSymbol, TODO: ObjectSymbol
59 'Literal',
60]
63@export
64@unique
65class OperatorPrecedence(IntEnum):
66 """
67 An enumeration of VHDL's operator precedence levels, from loosest to tightest binding.
69 The levels follow IEEE Std 1076-2008, clause 9.2. A range and a conditional expression are no operators, but bind
70 looser than every operator.
71 """
73 Range = 0 #: Range with direction ``to`` or ``downto``.
74 Conditional = 1 #: Conditional expression (``when`` ... ``else``).
75 Logical = 2 #: Binary logical operators, e.g. ``and``.
76 Relational = 3 #: Relational operators, e.g. ``=`` or ``?=``.
77 Shift = 4 #: Shift and rotate operators, e.g. ``sll``.
78 Adding = 5 #: Adding operators (``+``, ``-``, ``&``) and signs (unary ``+``, ``-``).
79 Multiplying = 6 #: Multiplying operators, e.g. ``*`` or ``mod``.
80 Miscellaneous = 7 #: Exponentiation (``**``), ``abs``, ``not`` and unary logical operators.
81 Primary = 8 #: Primaries, e.g. names, literals, aggregates or parenthesized expressions.
84@export
85@abstractclass
86class BaseExpression(ModelEntity):
87 """
88 Represents the base-class of all expressions.
90 .. seealso::
92 * :class:`Literal <pyVHDLModel.Expression.Literal>`
93 * :class:`Unary expression <pyVHDLModel.Expression.UnaryExpression>`
94 * :class:`Binary expression <pyVHDLModel.Expression.BinaryExpression>`
95 * :class:`Qualified expression <pyVHDLModel.Expression.QualifiedExpression>`
96 * :class:`Ternary expression <pyVHDLModel.Expression.TernaryExpression>`
97 * :class:`Function call <pyVHDLModel.Expression.FunctionCall>`
98 * :class:`Allocation <pyVHDLModel.Expression.Allocation>`
99 * :class:`Aggregate <pyVHDLModel.Expression.Aggregate>`
100 """
103@export
104@abstractclass
105class Literal(BaseExpression):
106 """
107 Represents the base-class of all literals.
109 A literal is an expression denoting a value written directly in the source.
111 .. seealso::
113 * :class:`Null literal <pyVHDLModel.Expression.NullLiteral>`
114 * :class:`Enumeration literal <pyVHDLModel.Expression.EnumerationLiteral>`
115 * :class:`Numeric literal <pyVHDLModel.Expression.NumericLiteral>`
116 * :class:`Character literal <pyVHDLModel.Expression.CharacterLiteral>`
117 * :class:`String literal <pyVHDLModel.Expression.StringLiteral>`
118 * :class:`Bit string literal <pyVHDLModel.Expression.BitStringLiteral>`
119 """
122@export
123class NullLiteral(Literal):
124 """
125 Represents a ``null`` literal.
127 A null literal denotes the null value of an access type.
129 .. admonition:: Example
131 .. code-block:: VHDL
133 p := null;
134 -- ^^^^ <- the literal
135 """
136 def Copy(self) -> Self:
137 """
138 Create a copy of this null literal.
140 The copy has no parent.
142 :returns: The new null literal.
143 """
144 return self.__class__()
146 def Visit(self, visitor: Visitor) -> None:
147 """
148 Walk this null literal with a visitor.
150 :param visitor: The visitor receiving the events.
151 """
152 visitor.VisitNullLiteral(self)
153 visitor.DepartNullLiteral(self)
155 def __str__(self) -> str:
156 """
157 Formats the null literal.
159 **Format:** ``null``
161 :returns: Formatted null literal.
162 """
163 return "null"
166@export
167class EnumerationLiteral(Literal):
168 """
169 Represents an enumeration literal.
171 The literal's name is available as :data:`Value`.
173 .. admonition:: Example
175 .. code-block:: VHDL
177 st <= Idle;
178 -- ^^^^ <- Value
179 """
180 _value: str #: The enumeration literal's name.
182 def __init__(self, value: str, parent: Nullable[ModelEntity] = None) -> None:
183 """
184 Initializes an enumeration literal.
186 :param value: The enumeration literal's name.
187 :param parent: The parent model entity of this entity.
188 """
189 super().__init__(parent)
191 self._value = value
193 @readonly
194 def Value(self) -> str:
195 """
196 Read-only property to access the value (:attr:`_value`).
198 :returns: The value.
199 """
200 return self._value
202 def Copy(self) -> Self:
203 """
204 Create a copy of this enumeration literal.
206 The copy has no parent.
208 :returns: The new enumeration literal.
209 """
210 return self.__class__(self._value)
212 def Visit(self, visitor: Visitor) -> None:
213 """
214 Walk this enumeration literal with a visitor.
216 :param visitor: The visitor receiving the events.
217 """
218 visitor.VisitEnumerationLiteral(self)
219 visitor.DepartEnumerationLiteral(self)
221 def __str__(self) -> str:
222 """
223 Formats the enumeration literal.
225 **Format:** ``idle``
227 :returns: Formatted enumeration literal.
228 """
229 return self._value
232@export
233@abstractclass
234class NumericLiteral(Literal):
235 """
236 Represents the base-class of all numeric literals.
238 Integer, floating-point and physical literals are numeric.
240 .. seealso::
242 * :class:`Integer literal <pyVHDLModel.Expression.IntegerLiteral>`
243 * :class:`Floating point literal <pyVHDLModel.Expression.FloatingPointLiteral>`
244 * :class:`Physical literal <pyVHDLModel.Expression.PhysicalLiteral>`
245 """
248@export
249class IntegerLiteral(NumericLiteral):
250 """
251 Represents an integer literal.
253 The literal's value is available as :data:`Value`.
255 .. admonition:: Example
257 .. code-block:: VHDL
259 res := a + 42;
260 -- ^^ <- Value
261 """
262 _value: int #: The literal's integer value.
264 def __init__(self, value: int) -> None:
265 """
266 Initializes an integer literal.
268 :param value: The literal's integer value.
269 """
270 super().__init__()
271 self._value = value
273 @readonly
274 def Value(self) -> int:
275 """
276 Read-only property to access the value (:attr:`_value`).
278 :returns: The value.
279 """
280 return self._value
282 def Copy(self) -> Self:
283 """
284 Create a copy of this integer literal.
286 The copy has no parent.
288 :returns: The new integer literal.
289 """
290 return self.__class__(self._value)
292 def Visit(self, visitor: Visitor) -> None:
293 """
294 Walk this integer literal with a visitor.
296 :param visitor: The visitor receiving the events.
297 """
298 visitor.VisitIntegerLiteral(self)
299 visitor.DepartIntegerLiteral(self)
301 def __str__(self) -> str:
302 """
303 Formats the integer literal.
305 **Format:** ``42``
307 :returns: Formatted integer literal.
308 """
309 return str(self._value)
312@export
313class FloatingPointLiteral(NumericLiteral):
314 """
315 Represents a floating-point literal.
317 The literal's value is available as :data:`Value`.
319 .. admonition:: Example
321 .. code-block:: VHDL
323 r <= 3.14;
324 -- ^^^^ <- Value
325 """
326 _value: float #: The literal's floating-point value.
328 def __init__(self, value: float) -> None:
329 """
330 Initializes a floating-point literal.
332 :param value: The literal's floating-point value.
333 """
334 super().__init__()
335 self._value = value
337 @readonly
338 def Value(self) -> float:
339 """
340 Read-only property to access the value (:attr:`_value`).
342 :returns: The value.
343 """
344 return self._value
346 def Copy(self) -> Self:
347 """
348 Create a copy of this floating-point literal.
350 The copy has no parent.
352 :returns: The new floating-point literal.
353 """
354 return self.__class__(self._value)
356 def Visit(self, visitor: Visitor) -> None:
357 """
358 Walk this floating-point literal with a visitor.
360 :param visitor: The visitor receiving the events.
361 """
362 visitor.VisitFloatingPointLiteral(self)
363 visitor.DepartFloatingPointLiteral(self)
365 def __str__(self) -> str:
366 """
367 Formats the floating-point literal.
369 **Format:** ``3.5``
371 :returns: Formatted floating-point literal.
372 """
373 return str(self._value)
376@export
377@abstractclass
378class PhysicalLiteral(NumericLiteral):
379 """
380 Represents the base-class of all physical literals.
382 A physical literal combines a numeric value with a unit name (:data:`UnitName`).
384 .. admonition:: Example
386 .. code-block:: VHDL
388 t <= 10 ns;
389 -- ^^ <- the value
390 -- ^^ <- UnitName
392 .. seealso::
394 * :class:`Physical integer literal <pyVHDLModel.Expression.PhysicalIntegerLiteral>`
395 * :class:`Physical floating literal <pyVHDLModel.Expression.PhysicalFloatingLiteral>`
396 """
397 _unitName: str #: The name of the physical unit the value is given in.
399 def __init__(self, unitName: str) -> None:
400 """
401 Initializes a physical literal.
403 :param unitName: The name of the physical unit the value is given in.
404 """
405 super().__init__()
406 self._unitName = unitName
408 @readonly
409 def UnitName(self) -> str:
410 """
411 Read-only property to access the unit name (:attr:`_unitName`).
413 :returns: The unit name.
414 """
415 return self._unitName
417 def __str__(self) -> str:
418 """
419 Formats the physical literal.
421 **Format:** ``10 ns``
423 :returns: Formatted physical literal.
424 """
425 return f"{self._value} {self._unitName}"
428@export
429class PhysicalIntegerLiteral(PhysicalLiteral):
430 """
431 Represents a physical literal with an integer value.
433 Value (:data:`Value`) and unit name (:data:`UnitName`) are available separately.
435 .. admonition:: Example
437 .. code-block:: VHDL
439 t <= 10 ns;
440 -- ^^ <- Value
441 -- ^^ <- UnitName
442 """
443 _value: int #: The literal's integer value, in units of :attr:`_unitName`.
445 def __init__(self, value: int, unitName: str) -> None:
446 """
447 Initializes a physical literal with an integer value.
449 :param value: The literal's integer value, in units of :attr:`_unitName`.
450 :param unitName: The name of the physical unit the value is given in.
451 """
452 super().__init__(unitName)
453 self._value = value
455 @readonly
456 def Value(self) -> int:
457 """
458 Read-only property to access the value (:attr:`_value`).
460 :returns: The value.
461 """
462 return self._value
464 def Copy(self) -> Self:
465 """
466 Create a copy of this physical literal.
468 The copy has no parent.
470 :returns: The new physical literal.
471 """
472 return self.__class__(self._value, self._unitName)
474 def Visit(self, visitor: Visitor) -> None:
475 """
476 Walk this physical literal with an integer value with a visitor.
478 :param visitor: The visitor receiving the events.
479 """
480 visitor.VisitPhysicalIntegerLiteral(self)
481 visitor.DepartPhysicalIntegerLiteral(self)
484@export
485class PhysicalFloatingLiteral(PhysicalLiteral):
486 """
487 Represents a physical literal with a floating-point value.
489 Value (:data:`Value`) and unit name (:data:`UnitName`) are available separately.
491 .. admonition:: Example
493 .. code-block:: VHDL
495 t <= 1.5 ns;
496 -- ^^^ <- Value
497 -- ^^ <- UnitName
498 """
499 _value: float #: The literal's floating-point value, in units of :attr:`_unitName`.
501 def __init__(self, value: float, unitName: str) -> None:
502 """
503 Initializes a physical literal with a floating-point value.
505 :param value: The literal's floating-point value, in units of :attr:`_unitName`.
506 :param unitName: The name of the physical unit the value is given in.
507 """
508 super().__init__(unitName)
509 self._value = value
511 @readonly
512 def Value(self) -> float:
513 """
514 Read-only property to access the value (:attr:`_value`).
516 :returns: The value.
517 """
518 return self._value
520 def Copy(self) -> Self:
521 """
522 Create a copy of this physical literal.
524 The copy has no parent.
526 :returns: The new physical literal.
527 """
528 return self.__class__(self._value, self._unitName)
530 def Visit(self, visitor: Visitor) -> None:
531 """
532 Walk this physical literal with a floating-point value with a visitor.
534 :param visitor: The visitor receiving the events.
535 """
536 visitor.VisitPhysicalFloatingLiteral(self)
537 visitor.DepartPhysicalFloatingLiteral(self)
540@export
541class CharacterLiteral(Literal):
542 """
543 Represents a character literal.
545 The literal's character is available as :data:`Value`. It is the bare character without the enclosing apostrophes:
546 ``a`` for the character literal ``'a'``.
548 .. admonition:: Example
550 .. code-block:: VHDL
552 ch <= 'a';
553 -- ^ <- Value
554 """
555 _value: str #: The literal's character value without apostrophes.
557 def __init__(self, value: str) -> None:
558 """
559 Initializes a character literal.
561 :param value: The literal's character value without apostrophes.
562 :raises ValueError: If parameter 'value' is None.
563 :raises TypeError: If parameter 'value' is not of type :class:`str`.
564 :raises ValueError: If parameter 'value' is not a single character.
565 """
566 super().__init__()
568 if value is None:
569 raise ValueError("Parameter 'value' is None.")
570 elif not isinstance(value, str):
571 ex = TypeError("Parameter 'value' is not of type 'str'.")
572 ex.add_note(f"Got type '{getFullyQualifiedName(value)}'.")
573 raise ex
574 elif len(value) != 1:
575 ex = ValueError("Parameter 'value' is not a single character.")
576 ex.add_note(f"Got value '{value}'.")
577 ex.add_note("Pass the character without apostrophes.")
578 raise ex
580 self._value = value
582 @readonly
583 def Value(self) -> str:
584 """
585 Read-only property to access the value (:attr:`_value`).
587 :returns: The value.
588 """
589 return self._value
591 def Copy(self) -> Self:
592 """
593 Create a copy of this character literal.
595 The copy has no parent.
597 :returns: The new character literal.
598 """
599 return self.__class__(self._value)
601 def Visit(self, visitor: Visitor) -> None:
602 """
603 Walk this character literal with a visitor.
605 :param visitor: The visitor receiving the events.
606 """
607 visitor.VisitCharacterLiteral(self)
608 visitor.DepartCharacterLiteral(self)
610 def __str__(self) -> str:
611 """
612 Formats the character literal.
614 **Format:** ``a``
616 :returns: Formatted character literal.
617 """
618 return str(self._value)
621@export
622class StringLiteral(Literal):
623 """
624 Represents a string literal.
626 The literal's text is available as :data:`Value`.
628 .. admonition:: Example
630 .. code-block:: VHDL
632 txt <= "text";
633 -- ^^^^^^ <- Value
634 """
635 _value: str #: The literal's string value, without the enclosing double quotes.
637 def __init__(self, value: str) -> None:
638 """
639 Initializes a string literal.
641 :param value: The literal's string value, without the enclosing double quotes.
642 """
643 super().__init__()
644 self._value = value
646 @readonly
647 def Value(self) -> str:
648 """
649 Read-only property to access the value (:attr:`_value`).
651 :returns: The value.
652 """
653 return self._value
655 def Copy(self) -> Self:
656 """
657 Create a copy of this string literal.
659 The copy has no parent.
661 :returns: The new string literal.
662 """
663 return self.__class__(self._value)
665 def Visit(self, visitor: Visitor) -> None:
666 """
667 Walk this string literal with a visitor.
669 :param visitor: The visitor receiving the events.
670 """
671 visitor.VisitStringLiteral(self)
672 visitor.DepartStringLiteral(self)
674 def __str__(self) -> str:
675 """
676 Formats the string literal.
678 **Format:** ``"hello"``
680 :returns: Formatted string literal.
681 """
682 return "\"" + self._value + "\""
685@export
686class BitStringBase(Flag):
687 """
688 Represents the base of a bit string literal: binary, octal, decimal or hexadecimal.
689 """
690 NoBase = 0
691 Binary = 2
692 Octal = 8
693 Decimal = 10
694 Hexadecimal = 16
695 Unsigned = 32
696 Signed = 64
699@export
700@abstractclass
701class BitStringLiteral(Literal):
702 """
703 Represents the base-class of all bit string literals.
705 Besides the literal as written (:data:`Value`), the bits are available in binary form
706 (:data:`BinaryValue`, :data:`Bits`), together with the literal's length (:data:`Length`) and
707 whether it is signed (:data:`IsSigned`).
709 The binary form follows IEEE Std 1076-2008, clause 15.8. It is computed on first access of :data:`BinaryValue` or
710 :data:`Bits`, so a literal violating these rules can still be constructed, copied and formatted.
712 .. admonition:: Example
714 .. code-block:: VHDL
716 res := b"10100000";
717 -- ^^^^^^^^^^^ <- Value
719 .. seealso::
721 * :class:`Binary bit string literal <pyVHDLModel.Expression.BinaryBitStringLiteral>`
722 * :class:`Octal bit string literal <pyVHDLModel.Expression.OctalBitStringLiteral>`
723 * :class:`Decimal bit string literal <pyVHDLModel.Expression.DecimalBitStringLiteral>`
724 * :class:`Hexadecimal bit string literal <pyVHDLModel.Expression.HexadecimalBitStringLiteral>`
725 """
726 _BASE: ClassVar[BitStringBase] = BitStringBase.NoBase #: The base this literal is written in.
728 _value: str #: The literal as written in the source, without the enclosing double quotes.
729 _binaryValue: Nullable[str] #: The literal's string value, one character per bit, or ``None`` until computed.
730 _length: Nullable[int] #: The explicitly given length, or ``None`` if the literal has no length specification.
731 _isSigned: Nullable[bool] #: ``True`` if signed, ``False`` if unsigned, ``None`` if unspecified.
733 def __init__(self, value: str, length: Nullable[int] = None, isSigned: Nullable[bool] = None) -> None:
734 """
735 Initializes a bit string literal.
737 :param value: The literal as written in the source, without the enclosing double quotes.
738 :param length: The explicitly given length, or ``None`` if the literal has no length specification.
739 :param isSigned: ``True`` if signed, ``False`` if unsigned, ``None`` if unspecified.
740 :raises ValueError: If parameter 'value' is None.
741 :raises TypeError: If parameter 'value' is not of type :class:`str`.
742 :raises TypeError: If parameter 'length' is not of type :class:`int`.
743 :raises ValueError: If parameter 'length' is negative.
744 :raises TypeError: If parameter 'isSigned' is not of type :class:`bool`.
745 """
746 super().__init__()
748 if value is None:
749 raise ValueError("Parameter 'value' is None.")
750 elif not isinstance(value, str):
751 ex = TypeError("Parameter 'value' is not of type 'str'.")
752 ex.add_note(f"Got type '{getFullyQualifiedName(value)}'.")
753 raise ex
755 if length is not None and not isinstance(length, int):
756 ex = TypeError("Parameter 'length' is not of type 'int'.")
757 ex.add_note(f"Got type '{getFullyQualifiedName(length)}'.")
758 raise ex
759 elif length is not None and length < 0:
760 ex = ValueError("Parameter 'length' is negative.")
761 ex.add_note(f"Got value '{length}'.")
762 raise ex
764 if isSigned is not None and not isinstance(isSigned, bool):
765 ex = TypeError("Parameter 'isSigned' is not of type 'bool'.")
766 ex.add_note(f"Got type '{getFullyQualifiedName(isSigned)}'.")
767 raise ex
769 self._value = value
770 self._binaryValue = None
771 self._length = length
772 self._isSigned = isSigned
774 @readonly
775 def Value(self) -> str:
776 """
777 Read-only property to access the value (:attr:`_value`).
779 :returns: The value.
780 """
781 return self._value
783 @readonly
784 def BinaryValue(self) -> str:
785 """
786 Read-only property to return the literal's string value, one character per bit (:attr:`_binaryValue`).
788 The value follows IEEE Std 1076-2008, clause 15.8. It is computed from :data:`Value`, the base, :data:`Length`
789 and :data:`IsSigned` on first access and cached:
791 1. Underscores are removed.
792 2. Expansion:
794 * Binary, octal and hexadecimal: each digit valid for the base is replaced by its 1, 3 or 4 bits; hexadecimal
795 digits are case-insensitive. Each other graphic character, e.g. ``X``, ``Z`` or ``-``, is repeated 1, 3 or 4
796 times, keeping its case.
797 * Decimal: the digits are converted to binary with the minimal number of bits (none for ``0``).
799 3. With a length larger than the expanded value, the value is padded on the left: with ``0`` if unsigned or
800 unspecified, with the leftmost character if signed.
801 4. With a length smaller than the expanded value, leftmost characters are deleted: only ``0`` if unsigned or
802 unspecified, only copies of the leftmost remaining character if signed.
804 Example: ``12sx"F5"`` |rarr| ``111111110101``.
806 :returns: The literal's string value, one character per bit.
807 :raises LiteralError: If the value starts or ends with an underscore or contains two consecutive underscores.
808 :raises LiteralError: If a decimal literal is signed or unsigned.
809 :raises LiteralError: If a decimal literal contains a character other than a digit or an underscore.
810 :raises LiteralError: If a digit is not allowed in the base, e.g. ``2`` in a binary literal.
811 :raises LiteralError: If the value contains a non-graphic character.
812 :raises LiteralError: If a signed literal with an empty expanded value has a non-zero length.
813 :raises LiteralError: If the length of an unsigned or unspecified literal truncates a character other than
814 ``0``. |br|
815 Only leading '0' characters can be truncated.
816 :raises LiteralError: If the length of a signed literal truncates a character other than the sign. |br|
817 Only copies of the leftmost remaining character can be truncated.
818 """
819 if self._binaryValue is not None:
820 return self._binaryValue
822 if self._value.startswith("_") or self._value.endswith("_") or "__" in self._value:
823 ex = LiteralError("Bit string literal has a leading, trailing or double underscore.", literal=self)
824 ex.add_note(f"Got value '{self}'.")
825 raise ex
827 simplifiedValue = self._value.replace("_", "")
828 radix = self._BASE.value
830 if self._BASE is BitStringBase.Decimal:
831 if self._isSigned is not None:
832 ex = LiteralError("Decimal bit string literal can't be signed or unsigned.", literal=self)
833 ex.add_note(f"Got value '{self}'.")
834 raise ex
836 for character in simplifiedValue:
837 if character not in "0123456789":
838 ex = LiteralError("Decimal bit string literal contains a character other than a digit.", literal=self)
839 ex.add_note(f"Got character '{character}' in value '{self}'.")
840 raise ex
842 number = 0 if simplifiedValue == "" else int(simplifiedValue)
843 expandedValue = "" if number == 0 else f"{number:b}"
844 else:
845 bitsPerDigit = radix.bit_length() - 1
846 bitList = []
847 for character in simplifiedValue:
848 if character in "0123456789":
849 digit = int(character)
850 if digit >= radix:
851 ex = LiteralError(f"Bit string literal contains a digit not allowed in base {radix}.", literal=self)
852 ex.add_note(f"Got digit '{character}' in value '{self}'.")
853 raise ex
854 elif radix == 16 and character in "abcdefABCDEF":
855 digit = int(character, 16)
856 elif 32 <= ord(character) <= 126 or 160 <= ord(character) <= 255:
857 bitList.append(character * bitsPerDigit)
858 continue
859 else:
860 ex = LiteralError("Bit string literal contains a non-graphic character.", literal=self)
861 ex.add_note(f"Got value {str(self)!r}.")
862 raise ex
864 bitList.append(f"{digit:0{bitsPerDigit}b}")
866 expandedValue = "".join(bitList)
868 expandedLength = len(expandedValue)
869 if self._length is None or self._length == expandedLength:
870 binaryValue = expandedValue
871 elif self._length > expandedLength:
872 if self._isSigned is not True:
873 padding = "0"
874 elif expandedLength == 0:
875 ex = LiteralError("Signed bit string literal with an empty value can't be extended.", literal=self)
876 ex.add_note(f"Got value '{self}'.")
877 raise ex
878 else:
879 padding = expandedValue[0]
881 binaryValue = padding * (self._length - expandedLength) + expandedValue
882 else:
883 deletedCount = expandedLength - self._length
884 deletedValue = expandedValue[:deletedCount]
885 binaryValue = expandedValue[deletedCount:]
886 if self._isSigned is not True:
887 padding = "0"
888 elif self._length == 0:
889 padding = ""
890 else:
891 padding = binaryValue[0]
893 if deletedValue != padding * deletedCount:
894 ex = LiteralError(f"Bit string literal's length {self._length} truncates significant characters.", literal=self)
895 ex.add_note(f"Got value '{self}' expanded to '{expandedValue}'.")
896 if self._isSigned is True:
897 ex.add_note("Only copies of the leftmost remaining character can be truncated.")
898 else:
899 ex.add_note("Only leading '0' characters can be truncated.")
900 raise ex
902 self._binaryValue = binaryValue
903 return binaryValue
905 @readonly
906 def Bits(self) -> int:
907 """
908 Read-only property to return the number of bits the literal represents.
910 This is the length of :data:`BinaryValue`, computed the same way, so the same exceptions apply.
912 :returns: The number of bits.
913 """
914 return len(self.BinaryValue)
916 @readonly
917 def Length(self) -> Nullable[int]:
918 """
919 Read-only property to access the length (:attr:`_length`).
921 :returns: The length, or ``None`` if not set.
922 """
923 return self._length
925 @readonly
926 def IsSigned(self) -> Nullable[bool]:
927 """
928 Check if the bit string literal is signed (:attr:`_isSigned`).
930 :returns: ``True``, if the literal is signed; ``False``, if unsigned; ``None``, if unspecified.
931 """
932 return self._isSigned
934 def Copy(self) -> Self:
935 """
936 Create a copy of this bit string literal.
938 The copy has no parent.
940 :returns: The new bit string literal.
941 """
942 return self.__class__(self._value, self._length, self._isSigned)
944 def Visit(self, visitor: Visitor) -> None:
945 """
946 Walk this bit string literal with a visitor.
948 :param visitor: The visitor receiving the events.
949 """
950 visitor.VisitBitStringLiteral(self)
951 visitor.DepartBitStringLiteral(self)
953 def __str__(self) -> str:
954 """
955 Formats the bit string literal.
957 **Format:** ``8ub"10100000"``
959 The length and the signedness marker (``s``/``u``) are omitted when unspecified.
961 :returns: Formatted bit string literal.
962 """
963 signed = "" if self._isSigned is None else "s" if self._isSigned is True else "u"
964 if self._BASE is BitStringBase.NoBase: 964 ↛ 965line 964 didn't jump to line 965 because the condition on line 964 was never true
965 base = ""
966 elif self._BASE is BitStringBase.Binary:
967 base = "b"
968 elif self._BASE is BitStringBase.Octal:
969 base = "o"
970 elif self._BASE is BitStringBase.Decimal:
971 base = "d"
972 elif self._BASE is BitStringBase.Hexadecimal: 972 ↛ 974line 972 didn't jump to line 974 because the condition on line 972 was always true
973 base = "x"
974 length = "" if self._length is None else str(self._length)
975 return length + signed + base + "\"" + self._value + "\""
978@export
979class BinaryBitStringLiteral(BitStringLiteral):
980 """
981 Represents a bit string literal written in base 2.
983 .. admonition:: Example
985 .. code-block:: VHDL
987 res := b"10100000";
988 -- ^^^^^^^^^^^ <- Value
989 """
990 _BASE: ClassVar[BitStringBase] = BitStringBase.Binary #: The base this literal is written in.
993@export
994class OctalBitStringLiteral(BitStringLiteral):
995 """
996 Represents a bit string literal written in base 8.
998 Each digit contributes three bits.
1000 .. admonition:: Example
1002 .. code-block:: VHDL
1004 res := o"240";
1005 -- ^^^^^^ <- Value
1006 """
1007 _BASE: ClassVar[BitStringBase] = BitStringBase.Octal #: The base this literal is written in.
1010@export
1011class DecimalBitStringLiteral(BitStringLiteral):
1012 """
1013 Represents a bit string literal written in base 10.
1015 .. admonition:: Example
1017 .. code-block:: VHDL
1019 res := d"160";
1020 -- ^^^^^^ <- Value
1021 """
1022 _BASE: ClassVar[BitStringBase] = BitStringBase.Decimal #: The base this literal is written in.
1025@export
1026class HexadecimalBitStringLiteral(BitStringLiteral):
1027 """
1028 Represents a bit string literal written in base 16.
1030 Each digit contributes four bits.
1032 .. admonition:: Example
1034 .. code-block:: VHDL
1036 res := x"A0";
1037 -- ^^^^^ <- Value
1038 """
1039 _BASE: ClassVar[BitStringBase] = BitStringBase.Hexadecimal #: The base this literal is written in.
1042@export
1043class ParenthesisExpression: #(Protocol):
1044 """
1045 Represents the base-class of expressions wrapped in parentheses.
1047 The operand is available as :data:`Operand`.
1049 .. seealso::
1051 * :class:`Sub expression <pyVHDLModel.Expression.SubExpression>`
1052 * :class:`Qualified expression <pyVHDLModel.Expression.QualifiedExpression>`
1053 """
1054 __slots__ = () # FIXME: use ExtendedType?
1056 @readonly
1057 def Operand(self) -> ExpressionUnion:
1058 """
1059 Read-only property to return the operand. A parenthesis expression has none of its own.
1061 :returns: The operand.
1062 """
1063 return None
1066@export
1067@abstractclass
1068class UnaryExpression(BaseExpression):
1069 """
1070 Represents the base-class of all unary expressions.
1072 The operand is available as :data:`Operand`.
1073 """
1075 _PRECEDENCE: ClassVar[OperatorPrecedence] #: The operator's precedence level.
1076 _FORMAT: ClassVar[tuple[str, str]] #: The operator's string representation as (prefix, suffix) of the operand.
1077 _RESERVED_WORD: ClassVar[Nullable[ReservedWord]] = None #: The operator's reserved word; ``None`` for a symbol (:attr:`_FORMAT`).
1078 _operand: ExpressionUnion #: The expression the operator is applied to.
1080 def __init__(self, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
1081 """
1082 Initializes a unary expression.
1084 :param operand: The expression the operator is applied to.
1085 :param parent: The parent model entity of this entity.
1086 """
1087 super().__init__(parent)
1089 self._operand = operand
1090 operand.Parent = self
1092 @readonly
1093 def Operand(self) -> ExpressionUnion:
1094 """
1095 Read-only property to access the operand (:attr:`_operand`).
1097 :returns: The operand.
1098 """
1099 return self._operand
1101 def Copy(self) -> Self:
1102 """
1103 Create a copy of this unary expression.
1105 The copy has no parent. Its operand is a copy of this expression's operand.
1107 :returns: The new unary expression.
1108 """
1109 return self.__class__(self._operand.Copy())
1111 def Visit(self, visitor: Visitor) -> None:
1112 """
1113 Walk this unary expression and its operand with a visitor.
1115 :param visitor: The visitor receiving the events.
1116 """
1117 visitor.VisitUnaryExpression(self)
1118 self._operand.Visit(visitor)
1119 visitor.DepartUnaryExpression(self)
1121 def __str__(self) -> str:
1122 """
1123 Formats the unary expression.
1125 **Format:** ``not operand``
1127 :returns: Formatted unary expression.
1128 """
1129 return f"{self._FORMAT[0]}{self._operand!s}{self._FORMAT[1]}"
1132@export
1133class NegationExpression(UnaryExpression):
1134 """
1135 Represents a negation (unary minus) expression.
1137 The operand is available as :data:`Operand`.
1139 .. admonition:: Example
1141 .. code-block:: VHDL
1143 res := - operand;
1144 -- ^^^^^^^^^ <- the expression
1145 -- ^^^^^^^ <- Operand
1146 """
1147 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Adding #: The operator's precedence level.
1148 _FORMAT: ClassVar[tuple[str, str]] = ("-", "") #: The operator's string fragments.
1150 def Visit(self, visitor: Visitor) -> None:
1151 """
1152 Walk this negation and its operand with a visitor.
1154 :param visitor: The visitor receiving the events.
1155 """
1156 visitor.VisitNegationExpression(self)
1157 self._operand.Visit(visitor)
1158 visitor.DepartNegationExpression(self)
1161@export
1162class IdentityExpression(UnaryExpression):
1163 """
1164 Represents an identity (unary plus) expression.
1166 The operand is available as :data:`Operand`.
1168 .. admonition:: Example
1170 .. code-block:: VHDL
1172 res := + operand;
1173 -- ^^^^^^^^^ <- the expression
1174 -- ^^^^^^^ <- Operand
1175 """
1176 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Adding #: The operator's precedence level.
1177 _FORMAT: ClassVar[tuple[str, str]] = ("+", "") #: The operator's string fragments.
1179 def Visit(self, visitor: Visitor) -> None:
1180 """
1181 Walk this identity and its operand with a visitor.
1183 :param visitor: The visitor receiving the events.
1184 """
1185 visitor.VisitIdentityExpression(self)
1186 self._operand.Visit(visitor)
1187 visitor.DepartIdentityExpression(self)
1190@export
1191class InverseExpression(UnaryExpression):
1192 """
1193 Represents a logical inversion expression (``not``).
1195 The operand is available as :data:`Operand`.
1197 .. admonition:: Example
1199 .. code-block:: VHDL
1201 res := not operand;
1202 -- ^^^^^^^^^^^ <- the expression
1203 -- ^^^^^^^ <- Operand
1204 """
1205 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1206 _FORMAT: ClassVar[tuple[str, str]] = ("not ", "") #: The operator's string fragments.
1207 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Not #: The operator's reserved word.
1210@export
1211class UnaryAndExpression(UnaryExpression):
1212 """
1213 Represents a ``and`` reduction expression.
1215 A reduction operator folds all elements of an array into a single value.
1216 The operand is available as :data:`Operand`.
1218 .. admonition:: Example
1220 .. code-block:: VHDL
1222 res := and operand;
1223 -- ^^^^^^^^^^^ <- the expression
1224 -- ^^^^^^^ <- Operand
1225 """
1226 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1227 _FORMAT: ClassVar[tuple[str, str]] = ("and ", "") #: The operator's string fragments.
1228 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.And #: The operator's reserved word.
1231@export
1232class UnaryNandExpression(UnaryExpression):
1233 """
1234 Represents a ``nand`` reduction expression.
1236 A reduction operator folds all elements of an array into a single value.
1237 The operand is available as :data:`Operand`.
1239 .. admonition:: Example
1241 .. code-block:: VHDL
1243 res := nand operand;
1244 -- ^^^^^^^^^^^^ <- the expression
1245 -- ^^^^^^^ <- Operand
1246 """
1247 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1248 _FORMAT: ClassVar[tuple[str, str]] = ("nand ", "") #: The operator's string fragments.
1249 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Nand #: The operator's reserved word.
1252@export
1253class UnaryOrExpression(UnaryExpression):
1254 """
1255 Represents a ``or`` reduction expression.
1257 A reduction operator folds all elements of an array into a single value.
1258 The operand is available as :data:`Operand`.
1260 .. admonition:: Example
1262 .. code-block:: VHDL
1264 res := or operand;
1265 -- ^^^^^^^^^^ <- the expression
1266 -- ^^^^^^^ <- Operand
1267 """
1268 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1269 _FORMAT: ClassVar[tuple[str, str]] = ("or ", "") #: The operator's string fragments.
1270 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Or #: The operator's reserved word.
1273@export
1274class UnaryNorExpression(UnaryExpression):
1275 """
1276 Represents a ``nor`` reduction expression.
1278 A reduction operator folds all elements of an array into a single value.
1279 The operand is available as :data:`Operand`.
1281 .. admonition:: Example
1283 .. code-block:: VHDL
1285 res := nor operand;
1286 -- ^^^^^^^^^^^ <- the expression
1287 -- ^^^^^^^ <- Operand
1288 """
1289 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1290 _FORMAT: ClassVar[tuple[str, str]] = ("nor ", "") #: The operator's string fragments.
1291 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Nor #: The operator's reserved word.
1294@export
1295class UnaryXorExpression(UnaryExpression):
1296 """
1297 Represents a ``xor`` reduction expression.
1299 A reduction operator folds all elements of an array into a single value.
1300 The operand is available as :data:`Operand`.
1302 .. admonition:: Example
1304 .. code-block:: VHDL
1306 res := xor operand;
1307 -- ^^^^^^^^^^^ <- the expression
1308 -- ^^^^^^^ <- Operand
1309 """
1310 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1311 _FORMAT: ClassVar[tuple[str, str]] = ("xor ", "") #: The operator's string fragments.
1312 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Xor #: The operator's reserved word.
1315@export
1316class UnaryXnorExpression(UnaryExpression):
1317 """
1318 Represents a ``xnor`` reduction expression.
1320 A reduction operator folds all elements of an array into a single value.
1321 The operand is available as :data:`Operand`.
1323 .. admonition:: Example
1325 .. code-block:: VHDL
1327 res := xnor operand;
1328 -- ^^^^^^^^^^^^ <- the expression
1329 -- ^^^^^^^ <- Operand
1330 """
1331 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1332 _FORMAT: ClassVar[tuple[str, str]] = ("xnor ", "") #: The operator's string fragments.
1333 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Xnor #: The operator's reserved word.
1336@export
1337class AbsoluteExpression(UnaryExpression):
1338 """
1339 Represents an absolute value expression (``abs``).
1341 The operand is available as :data:`Operand`.
1343 .. admonition:: Example
1345 .. code-block:: VHDL
1347 res := abs operand;
1348 -- ^^^^^^^^^^^ <- the expression
1349 -- ^^^^^^^ <- Operand
1350 """
1351 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1352 _FORMAT: ClassVar[tuple[str, str]] = ("abs ", "") #: The operator's string fragments.
1353 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Abs #: The operator's reserved word.
1356@export
1357class TypeConversion(UnaryExpression):
1358 """
1359 Represents a type conversion.
1361 A type conversion converts its operand (:data:`Operand`) to the target subtype
1362 (:data:`TargetSubtype`). Unlike every other :class:`UnaryExpression`, its "operator" is the target
1363 type name itself rather than a fixed string, so it carries its own subtype and renders itself.
1365 .. admonition:: Example
1367 .. code-block:: VHDL
1369 res := integer(val);
1370 -- ^^^^^^^ <- TargetSubtype
1371 -- ^^^ <- Operand
1372 """
1373 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Primary #: The operator's precedence level.
1375 _targetSubtype: SubtypeSymbol #: Reference to the subtype the expression is converted to.
1377 def __init__(self, targetSubtype: SubtypeSymbol, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
1378 """
1379 Initializes a type conversion.
1381 :param targetSubtype: Reference to the subtype the expression is converted to.
1382 :param operand: The expression the operator is applied to.
1383 :param parent: The parent model entity of this entity.
1384 """
1385 super().__init__(operand, parent)
1387 self._targetSubtype = targetSubtype
1388 targetSubtype.Parent = self
1390 @readonly
1391 def TargetSubtype(self) -> SubtypeSymbol:
1392 """
1393 Read-only property to access the target subtype (:attr:`_targetSubtype`).
1395 :returns: The target subtype.
1396 """
1397 return self._targetSubtype
1399 def Copy(self) -> Self:
1400 """
1401 Create a copy of this type conversion.
1403 The copy has no parent. Its target subtype and operand are copies of this conversion's target subtype and operand.
1405 :returns: The new type conversion.
1406 """
1407 return self.__class__(self._targetSubtype.Copy(), self._operand.Copy())
1409 def Visit(self, visitor: Visitor) -> None:
1410 """
1411 Walk this type conversion, its target subtype and its operand with a visitor.
1413 :param visitor: The visitor receiving the events.
1414 """
1415 visitor.VisitTypeConversion(self)
1416 self._targetSubtype.Visit(visitor)
1417 visitor.VisitLeftParenthesis(self)
1418 self._operand.Visit(visitor)
1419 visitor.DepartTypeConversion(self)
1421 def __str__(self) -> str:
1422 """
1423 Formats the type conversion.
1425 **Format:** ``integer(val)``
1427 :returns: Formatted type conversion.
1428 """
1429 return f"{self._targetSubtype!s}({self._operand!s})"
1432@export
1433class SubExpression(UnaryExpression, ParenthesisExpression):
1434 """
1435 Represents a parenthesized sub-expression.
1437 The operand is available as :data:`Operand`.
1439 .. admonition:: Example
1441 .. code-block:: VHDL
1443 res := (lhs + rhs);
1444 -- ^^^^^^^^^^^ <- the sub-expression
1445 -- ^^^^^^^^^ <- Operand
1446 """
1447 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Primary #: The operator's precedence level.
1448 _FORMAT: ClassVar[tuple[str, str]] = ("(", ")") #: The operator's string fragments.
1450 def Visit(self, visitor: Visitor) -> None:
1451 """
1452 Walk this sub-expression and its operand with a visitor.
1454 :param visitor: The visitor receiving the events.
1455 """
1456 visitor.VisitSubExpression(self)
1457 self._operand.Visit(visitor)
1458 visitor.DepartSubExpression(self)
1461@export
1462@abstractclass
1463class BinaryExpression(BaseExpression):
1464 """
1465 Represents the base-class of all binary expressions.
1467 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1469 .. seealso::
1471 * :class:`Range expression <pyVHDLModel.Expression.RangeExpression>`
1472 * :class:`Adding expression <pyVHDLModel.Expression.AddingExpression>`
1473 * :class:`Multiplying expression <pyVHDLModel.Expression.MultiplyingExpression>`
1474 * :class:`Logical expression <pyVHDLModel.Expression.LogicalExpression>`
1475 * :class:`Relational expression <pyVHDLModel.Expression.RelationalExpression>`
1476 * :class:`Shift expression <pyVHDLModel.Expression.ShiftExpression>`
1477 """
1479 _PRECEDENCE: ClassVar[OperatorPrecedence] #: The operator's precedence level.
1480 _FORMAT: ClassVar[tuple[str, str, str]] #: The operator's string representation as (prefix, infix, suffix).
1481 _RESERVED_WORD: ClassVar[Nullable[ReservedWord]] = None #: The operator's reserved word; ``None`` for a symbol (:attr:`_FORMAT`).
1482 _leftOperand: ExpressionUnion #: The expression left of the operator.
1483 _rightOperand: ExpressionUnion #: The expression right of the operator.
1485 def __init__(self, leftOperand: ExpressionUnion, rightOperand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
1486 """
1487 Initializes a binary expression.
1489 :param leftOperand: The expression left of the operator.
1490 :param rightOperand: The expression right of the operator.
1491 :param parent: The parent model entity of this entity.
1492 """
1493 super().__init__(parent)
1495 self._leftOperand = leftOperand
1496 leftOperand.Parent = self
1498 self._rightOperand = rightOperand
1499 rightOperand.Parent = self
1501 @readonly
1502 def LeftOperand(self) -> ExpressionUnion:
1503 """
1504 Read-only property to access the left operand (:attr:`_leftOperand`).
1506 :returns: The left operand.
1507 """
1508 return self._leftOperand
1510 @readonly
1511 def RightOperand(self) -> ExpressionUnion:
1512 """
1513 Read-only property to access the right operand (:attr:`_rightOperand`).
1515 :returns: The right operand.
1516 """
1517 return self._rightOperand
1519 def Copy(self) -> Self:
1520 """
1521 Create a copy of this binary expression.
1523 The copy has no parent. Its operands are copies of this expression's operands.
1525 :returns: The new binary expression.
1526 """
1527 return self.__class__(self._leftOperand.Copy(), self._rightOperand.Copy())
1529 def __str__(self) -> str:
1530 """
1531 Formats the binary expression.
1533 **Format:** ``lhs + rhs``
1535 :returns: Formatted binary expression.
1536 """
1537 return "{leftOperator}{leftOperand!s}{middleOperator}{rightOperand!s}{rightOperator}".format(
1538 leftOperator=self._FORMAT[0],
1539 leftOperand=self._leftOperand,
1540 middleOperator=self._FORMAT[1],
1541 rightOperand=self._rightOperand,
1542 rightOperator=self._FORMAT[2],
1543 )
1546@export
1547@abstractclass
1548class RangeExpression(BinaryExpression):
1549 """
1550 Represents the base-class of range expressions.
1552 A range has a direction (:data:`Direction`) and two bounds. Both operands are available as :data:`LeftOperand` and
1553 :data:`RightOperand`.
1555 .. seealso::
1557 * :class:`Ascending range expression <pyVHDLModel.Expression.AscendingRangeExpression>`
1558 * :class:`Descending range expression <pyVHDLModel.Expression.DescendingRangeExpression>`
1559 """
1560 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Range #: The operator's precedence level.
1561 _DIRECTION: ClassVar[Direction] #: The range's direction (``to`` or ``downto``).
1563 @readonly
1564 def Direction(self) -> Direction:
1565 """
1566 Read-only property to access the direction (:attr:`_DIRECTION`).
1568 :returns: The direction.
1569 """
1570 return self._DIRECTION
1572 def Visit(self, visitor: Visitor) -> None:
1573 """
1574 Walk this range expression and its bounds with a visitor.
1576 :param visitor: The visitor receiving the events.
1577 """
1578 visitor.VisitRangeExpression(self)
1579 self._leftOperand.Visit(visitor)
1580 visitor.VisitDirection(self)
1581 self._rightOperand.Visit(visitor)
1582 visitor.DepartRangeExpression(self)
1585@export
1586class AscendingRangeExpression(RangeExpression):
1587 """
1588 Represents an ascending range expression (``to``).
1590 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1592 .. admonition:: Example
1594 .. code-block:: VHDL
1596 res := v(0 to 3);
1597 -- ^^^^^^ <- the range
1598 -- ^ <- LeftOperand
1599 -- ^ <- RightOperand
1600 """
1601 _DIRECTION: ClassVar[Direction] = Direction.To #: The range's direction.
1602 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " to ", "") #: The operator's string fragments.
1605@export
1606class DescendingRangeExpression(RangeExpression):
1607 """
1608 Represents a descending range expression (``downto``).
1610 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1612 .. admonition:: Example
1614 .. code-block:: VHDL
1616 res := v(7 downto 4);
1617 -- ^^^^^^^^^^ <- the range
1618 -- ^ <- LeftOperand
1619 -- ^ <- RightOperand
1620 """
1621 _DIRECTION: ClassVar[Direction] = Direction.DownTo #: The range's direction.
1622 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " downto ", "") #: The operator's string fragments.
1625@export
1626@abstractclass
1627class AddingExpression(BinaryExpression):
1628 """
1629 Represents the base-class of all adding expressions: ``+``, ``-`` and ``&``.
1631 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1633 .. seealso::
1635 * :class:`Addition expression <pyVHDLModel.Expression.AdditionExpression>`
1636 * :class:`Subtraction expression <pyVHDLModel.Expression.SubtractionExpression>`
1637 * :class:`Concatenation expression <pyVHDLModel.Expression.ConcatenationExpression>`
1638 """
1639 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Adding #: The operator's precedence level.
1641 def Visit(self, visitor: Visitor) -> None:
1642 """
1643 Walk this adding expression and its operands with a visitor.
1645 :param visitor: The visitor receiving the events.
1646 """
1647 visitor.VisitAddingExpression(self)
1648 self._leftOperand.Visit(visitor)
1649 visitor.VisitOperator(self)
1650 self._rightOperand.Visit(visitor)
1651 visitor.DepartAddingExpression(self)
1654@export
1655class AdditionExpression(AddingExpression):
1656 """
1657 Represents an addition expression (``+``).
1659 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1661 .. admonition:: Example
1663 .. code-block:: VHDL
1665 res := lhs + rhs;
1666 -- ^^^^^^^^^ <- the expression
1667 -- ^^^ <- LeftOperand
1668 -- ^^^ <- RightOperand
1669 """
1670 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " + ", "") #: The operator's string fragments.
1673@export
1674class SubtractionExpression(AddingExpression):
1675 """
1676 Represents a subtraction expression (``-``).
1678 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1680 .. admonition:: Example
1682 .. code-block:: VHDL
1684 res := lhs - rhs;
1685 -- ^^^^^^^^^ <- the expression
1686 -- ^^^ <- LeftOperand
1687 -- ^^^ <- RightOperand
1688 """
1689 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " - ", "") #: The operator's string fragments.
1692@export
1693class ConcatenationExpression(AddingExpression):
1694 """
1695 Represents a concatenation expression (``&``).
1697 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1699 .. admonition:: Example
1701 .. code-block:: VHDL
1703 res := lhs & rhs;
1704 -- ^^^^^^^^^ <- the expression
1705 -- ^^^ <- LeftOperand
1706 -- ^^^ <- RightOperand
1707 """
1708 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " & ", "") #: The operator's string fragments.
1711@export
1712@abstractclass
1713class MultiplyingExpression(BinaryExpression):
1714 """
1715 Represents the base-class of all multiplying expressions: ``*``, ``/``, ``rem``, ``mod`` and ``**``.
1717 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1719 .. seealso::
1721 * :class:`Multiply expression <pyVHDLModel.Expression.MultiplyExpression>`
1722 * :class:`Division expression <pyVHDLModel.Expression.DivisionExpression>`
1723 * :class:`Remainder expression <pyVHDLModel.Expression.RemainderExpression>`
1724 * :class:`Modulo expression <pyVHDLModel.Expression.ModuloExpression>`
1725 * :class:`Exponentiation expression <pyVHDLModel.Expression.ExponentiationExpression>`
1726 """
1727 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Multiplying #: The operator's precedence level.
1729 def Visit(self, visitor: Visitor) -> None:
1730 """
1731 Walk this multiplying expression and its operands with a visitor.
1733 :param visitor: The visitor receiving the events.
1734 """
1735 visitor.VisitMultiplyingExpression(self)
1736 self._leftOperand.Visit(visitor)
1737 visitor.VisitOperator(self)
1738 self._rightOperand.Visit(visitor)
1739 visitor.DepartMultiplyingExpression(self)
1742@export
1743class MultiplyExpression(MultiplyingExpression):
1744 """
1745 Represents a multiplication expression (``*``).
1747 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1749 .. admonition:: Example
1751 .. code-block:: VHDL
1753 res := lhs * rhs;
1754 -- ^^^^^^^^^ <- the expression
1755 -- ^^^ <- LeftOperand
1756 -- ^^^ <- RightOperand
1757 """
1758 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " * ", "") #: The operator's string fragments.
1761@export
1762class DivisionExpression(MultiplyingExpression):
1763 """
1764 Represents a division expression (``/``).
1766 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1768 .. admonition:: Example
1770 .. code-block:: VHDL
1772 res := lhs / rhs;
1773 -- ^^^^^^^^^ <- the expression
1774 -- ^^^ <- LeftOperand
1775 -- ^^^ <- RightOperand
1776 """
1777 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " / ", "") #: The operator's string fragments.
1780@export
1781class RemainderExpression(MultiplyingExpression):
1782 """
1783 Represents a remainder expression (``rem``).
1785 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1787 .. admonition:: Example
1789 .. code-block:: VHDL
1791 res := lhs rem rhs;
1792 -- ^^^^^^^^^^^ <- the expression
1793 -- ^^^ <- LeftOperand
1794 -- ^^^ <- RightOperand
1795 """
1796 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " rem ", "") #: The operator's string fragments.
1797 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Rem #: The operator's reserved word.
1800@export
1801class ModuloExpression(MultiplyingExpression):
1802 """
1803 Represents a modulo expression (``mod``).
1805 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1807 .. admonition:: Example
1809 .. code-block:: VHDL
1811 res := lhs mod rhs;
1812 -- ^^^^^^^^^^^ <- the expression
1813 -- ^^^ <- LeftOperand
1814 -- ^^^ <- RightOperand
1815 """
1816 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " mod ", "") #: The operator's string fragments.
1817 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Mod #: The operator's reserved word.
1820@export
1821class ExponentiationExpression(MultiplyingExpression):
1822 """
1823 Represents an exponentiation expression (``**``).
1825 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1827 .. admonition:: Example
1829 .. code-block:: VHDL
1831 res := lhs ** rhs;
1832 -- ^^^^^^^^^^ <- the expression
1833 -- ^^^ <- LeftOperand
1834 -- ^^^ <- RightOperand
1835 """
1836 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Miscellaneous #: The operator's precedence level.
1837 _FORMAT: ClassVar[tuple[str, str, str]] = ("", "**", "") #: The operator's string fragments.
1839 def Visit(self, visitor: Visitor) -> None:
1840 """
1841 Walk this exponentiation and its operands with a visitor.
1843 :param visitor: The visitor receiving the events.
1844 """
1845 visitor.VisitExponentiationExpression(self)
1846 self._leftOperand.Visit(visitor)
1847 visitor.VisitOperator(self)
1848 self._rightOperand.Visit(visitor)
1849 visitor.DepartExponentiationExpression(self)
1852@export
1853@abstractclass
1854class LogicalExpression(BinaryExpression):
1855 """
1856 Represents the base-class of all binary logical expressions.
1858 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1860 .. seealso::
1862 * :class:`And expression <pyVHDLModel.Expression.AndExpression>`
1863 * :class:`Nand expression <pyVHDLModel.Expression.NandExpression>`
1864 * :class:`Or expression <pyVHDLModel.Expression.OrExpression>`
1865 * :class:`Nor expression <pyVHDLModel.Expression.NorExpression>`
1866 * :class:`Xor expression <pyVHDLModel.Expression.XorExpression>`
1867 * :class:`Xnor expression <pyVHDLModel.Expression.XnorExpression>`
1868 """
1869 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Logical #: The operator's precedence level.
1871 def Visit(self, visitor: Visitor) -> None:
1872 """
1873 Walk this logical expression and its operands with a visitor.
1875 :param visitor: The visitor receiving the events.
1876 """
1877 visitor.VisitLogicalExpression(self)
1878 self._leftOperand.Visit(visitor)
1879 visitor.VisitOperator(self)
1880 self._rightOperand.Visit(visitor)
1881 visitor.DepartLogicalExpression(self)
1884@export
1885class AndExpression(LogicalExpression):
1886 """
1887 Represents a logical ``and`` expression.
1889 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1891 .. admonition:: Example
1893 .. code-block:: VHDL
1895 res := lhs and rhs;
1896 -- ^^^^^^^^^^^ <- the expression
1897 -- ^^^ <- LeftOperand
1898 -- ^^^ <- RightOperand
1899 """
1900 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " and ", "") #: The operator's string fragments.
1901 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.And #: The operator's reserved word.
1904@export
1905class NandExpression(LogicalExpression):
1906 """
1907 Represents a logical ``nand`` expression.
1909 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1911 .. admonition:: Example
1913 .. code-block:: VHDL
1915 res := lhs nand rhs;
1916 -- ^^^^^^^^^^^^ <- the expression
1917 -- ^^^ <- LeftOperand
1918 -- ^^^ <- RightOperand
1919 """
1920 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " nand ", "") #: The operator's string fragments.
1921 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Nand #: The operator's reserved word.
1924@export
1925class OrExpression(LogicalExpression):
1926 """
1927 Represents a logical ``or`` expression.
1929 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1931 .. admonition:: Example
1933 .. code-block:: VHDL
1935 res := lhs or rhs;
1936 -- ^^^^^^^^^^ <- the expression
1937 -- ^^^ <- LeftOperand
1938 -- ^^^ <- RightOperand
1939 """
1940 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " or ", "") #: The operator's string fragments.
1941 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Or #: The operator's reserved word.
1944@export
1945class NorExpression(LogicalExpression):
1946 """
1947 Represents a logical ``nor`` expression.
1949 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1951 .. admonition:: Example
1953 .. code-block:: VHDL
1955 res := lhs nor rhs;
1956 -- ^^^^^^^^^^^ <- the expression
1957 -- ^^^ <- LeftOperand
1958 -- ^^^ <- RightOperand
1959 """
1960 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " nor ", "") #: The operator's string fragments.
1961 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Nor #: The operator's reserved word.
1964@export
1965class XorExpression(LogicalExpression):
1966 """
1967 Represents a logical ``xor`` expression.
1969 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1971 .. admonition:: Example
1973 .. code-block:: VHDL
1975 res := lhs xor rhs;
1976 -- ^^^^^^^^^^^ <- the expression
1977 -- ^^^ <- LeftOperand
1978 -- ^^^ <- RightOperand
1979 """
1980 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " xor ", "") #: The operator's string fragments.
1981 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Xor #: The operator's reserved word.
1984@export
1985class XnorExpression(LogicalExpression):
1986 """
1987 Represents a logical ``xnor`` expression.
1989 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
1991 .. admonition:: Example
1993 .. code-block:: VHDL
1995 res := lhs xnor rhs;
1996 -- ^^^^^^^^^^^^ <- the expression
1997 -- ^^^ <- LeftOperand
1998 -- ^^^ <- RightOperand
1999 """
2000 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " xnor ", "") #: The operator's string fragments.
2001 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Xnor #: The operator's reserved word.
2004@export
2005@abstractclass
2006class RelationalExpression(BinaryExpression):
2007 """
2008 Represents the base-class of all relational expressions.
2010 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2012 .. seealso::
2014 * :class:`Equal expression <pyVHDLModel.Expression.EqualExpression>`
2015 * :class:`Unequal expression <pyVHDLModel.Expression.UnequalExpression>`
2016 * :class:`Greater than expression <pyVHDLModel.Expression.GreaterThanExpression>`
2017 * :class:`Greater equal expression <pyVHDLModel.Expression.GreaterEqualExpression>`
2018 * :class:`Less than expression <pyVHDLModel.Expression.LessThanExpression>`
2019 * :class:`Less equal expression <pyVHDLModel.Expression.LessEqualExpression>`
2020 * :class:`Matching relational expression <pyVHDLModel.Expression.MatchingRelationalExpression>`
2021 """
2022 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Relational #: The operator's precedence level.
2024 def Visit(self, visitor: Visitor) -> None:
2025 """
2026 Walk this relational expression and its operands with a visitor.
2028 :param visitor: The visitor receiving the events.
2029 """
2030 visitor.VisitRelationalExpression(self)
2031 self._leftOperand.Visit(visitor)
2032 visitor.VisitOperator(self)
2033 self._rightOperand.Visit(visitor)
2034 visitor.DepartRelationalExpression(self)
2037@export
2038class EqualExpression(RelationalExpression):
2039 """
2040 Represents an equality expression (``=``).
2042 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2044 .. admonition:: Example
2046 .. code-block:: VHDL
2048 res := lhs = rhs;
2049 -- ^^^^^^^^^ <- the expression
2050 -- ^^^ <- LeftOperand
2051 -- ^^^ <- RightOperand
2052 """
2053 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " = ", "") #: The operator's string fragments.
2056@export
2057class UnequalExpression(RelationalExpression):
2058 """
2059 Represents an inequality expression (``/=``).
2061 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2063 .. admonition:: Example
2065 .. code-block:: VHDL
2067 res := lhs /= rhs;
2068 -- ^^^^^^^^^^ <- the expression
2069 -- ^^^ <- LeftOperand
2070 -- ^^^ <- RightOperand
2071 """
2072 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " /= ", "") #: The operator's string fragments.
2075@export
2076class GreaterThanExpression(RelationalExpression):
2077 """
2078 Represents a greater-than expression (``>``).
2080 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2082 .. admonition:: Example
2084 .. code-block:: VHDL
2086 res := lhs > rhs;
2087 -- ^^^^^^^^^ <- the expression
2088 -- ^^^ <- LeftOperand
2089 -- ^^^ <- RightOperand
2090 """
2091 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " > ", "") #: The operator's string fragments.
2094@export
2095class GreaterEqualExpression(RelationalExpression):
2096 """
2097 Represents a greater-or-equal expression (``>=``).
2099 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2101 .. admonition:: Example
2103 .. code-block:: VHDL
2105 res := lhs >= rhs;
2106 -- ^^^^^^^^^^ <- the expression
2107 -- ^^^ <- LeftOperand
2108 -- ^^^ <- RightOperand
2109 """
2110 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " >= ", "") #: The operator's string fragments.
2113@export
2114class LessThanExpression(RelationalExpression):
2115 """
2116 Represents a less-than expression (``<``).
2118 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2120 .. admonition:: Example
2122 .. code-block:: VHDL
2124 res := lhs < rhs;
2125 -- ^^^^^^^^^ <- the expression
2126 -- ^^^ <- LeftOperand
2127 -- ^^^ <- RightOperand
2128 """
2129 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " < ", "") #: The operator's string fragments.
2132@export
2133class LessEqualExpression(RelationalExpression):
2134 """
2135 Represents a less-or-equal expression (``<=``).
2137 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2139 .. admonition:: Example
2141 .. code-block:: VHDL
2143 res := lhs <= rhs;
2144 -- ^^^^^^^^^^ <- the expression
2145 -- ^^^ <- LeftOperand
2146 -- ^^^ <- RightOperand
2147 """
2148 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " <= ", "") #: The operator's string fragments.
2151@export
2152@abstractclass
2153class MatchingRelationalExpression(RelationalExpression):
2154 """
2155 Represents the base-class of all matching relational expressions.
2157 Matching operators return a ``bit``/``std_ulogic`` rather than a ``boolean``. Both operands are available as
2158 :data:`LeftOperand` and :data:`RightOperand`.
2160 .. seealso::
2162 * :class:`Matching equal expression <pyVHDLModel.Expression.MatchingEqualExpression>`
2163 * :class:`Matching unequal expression <pyVHDLModel.Expression.MatchingUnequalExpression>`
2164 * :class:`Matching greater than expression <pyVHDLModel.Expression.MatchingGreaterThanExpression>`
2165 * :class:`Matching greater equal expression <pyVHDLModel.Expression.MatchingGreaterEqualExpression>`
2166 * :class:`Matching less than expression <pyVHDLModel.Expression.MatchingLessThanExpression>`
2167 * :class:`Matching less equal expression <pyVHDLModel.Expression.MatchingLessEqualExpression>`
2168 """
2169 pass
2172@export
2173class MatchingEqualExpression(MatchingRelationalExpression):
2174 """
2175 Represents a matching equality expression (``?=``).
2177 Unlike ``=``, a matching operator returns a ``bit``/``std_ulogic``.
2178 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2180 .. admonition:: Example
2182 .. code-block:: VHDL
2184 res := lhs ?= rhs;
2185 -- ^^^^^^^^^^ <- the expression
2186 -- ^^^ <- LeftOperand
2187 -- ^^^ <- RightOperand
2188 """
2189 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?= ", "") #: The operator's string fragments.
2192@export
2193class MatchingUnequalExpression(MatchingRelationalExpression):
2194 """
2195 Represents a matching inequality expression (``?/=``).
2197 Unlike ``/=``, a matching operator returns a ``bit``/``std_ulogic``.
2198 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2200 .. admonition:: Example
2202 .. code-block:: VHDL
2204 res := lhs ?/= rhs;
2205 -- ^^^^^^^^^^^ <- the expression
2206 -- ^^^ <- LeftOperand
2207 -- ^^^ <- RightOperand
2208 """
2209 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?/= ", "") #: The operator's string fragments.
2212@export
2213class MatchingGreaterThanExpression(MatchingRelationalExpression):
2214 """
2215 Represents a matching greater-than expression (``?>``).
2217 Unlike ``>``, a matching operator returns a ``bit``/``std_ulogic``.
2218 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2220 .. admonition:: Example
2222 .. code-block:: VHDL
2224 res := lhs ?> rhs;
2225 -- ^^^^^^^^^^ <- the expression
2226 -- ^^^ <- LeftOperand
2227 -- ^^^ <- RightOperand
2228 """
2229 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?> ", "") #: The operator's string fragments.
2232@export
2233class MatchingGreaterEqualExpression(MatchingRelationalExpression):
2234 """
2235 Represents a matching greater-or-equal expression (``?>=``).
2237 Unlike ``>=``, a matching operator returns a ``bit``/``std_ulogic``.
2238 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2240 .. admonition:: Example
2242 .. code-block:: VHDL
2244 res := lhs ?>= rhs;
2245 -- ^^^^^^^^^^^ <- the expression
2246 -- ^^^ <- LeftOperand
2247 -- ^^^ <- RightOperand
2248 """
2249 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?>= ", "") #: The operator's string fragments.
2252@export
2253class MatchingLessThanExpression(MatchingRelationalExpression):
2254 """
2255 Represents a matching less-than expression (``?<``).
2257 Unlike ``<``, a matching operator returns a ``bit``/``std_ulogic``.
2258 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2260 .. admonition:: Example
2262 .. code-block:: VHDL
2264 res := lhs ?< rhs;
2265 -- ^^^^^^^^^^ <- the expression
2266 -- ^^^ <- LeftOperand
2267 -- ^^^ <- RightOperand
2268 """
2269 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?< ", "") #: The operator's string fragments.
2272@export
2273class MatchingLessEqualExpression(MatchingRelationalExpression):
2274 """
2275 Represents a matching less-or-equal expression (``?<=``).
2277 Unlike ``<=``, a matching operator returns a ``bit``/``std_ulogic``.
2278 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2280 .. admonition:: Example
2282 .. code-block:: VHDL
2284 res := lhs ?<= rhs;
2285 -- ^^^^^^^^^^^ <- the expression
2286 -- ^^^ <- LeftOperand
2287 -- ^^^ <- RightOperand
2288 """
2289 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ?<= ", "") #: The operator's string fragments.
2292@export
2293@abstractclass
2294class ShiftExpression(BinaryExpression):
2295 """
2296 Represents the base-class of all shift and rotate expressions.
2298 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2300 .. seealso::
2302 * :class:`Shift logic expression <pyVHDLModel.Expression.ShiftLogicExpression>`
2303 * :class:`Shift arithmetic expression <pyVHDLModel.Expression.ShiftArithmeticExpression>`
2304 * :class:`Rotate expression <pyVHDLModel.Expression.RotateExpression>`
2305 """
2306 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Shift #: The operator's precedence level.
2308 def Visit(self, visitor: Visitor) -> None:
2309 """
2310 Walk this shift or rotate expression and its operands with a visitor.
2312 :param visitor: The visitor receiving the events.
2313 """
2314 visitor.VisitShiftExpression(self)
2315 self._leftOperand.Visit(visitor)
2316 visitor.VisitOperator(self)
2317 self._rightOperand.Visit(visitor)
2318 visitor.DepartShiftExpression(self)
2321@export
2322@abstractclass
2323class ShiftLogicExpression(ShiftExpression):
2324 """
2325 Represents the base-class of the logical shift expressions ``srl`` and ``sll``.
2327 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2329 .. seealso::
2331 * :class:`Shift right logic expression <pyVHDLModel.Expression.ShiftRightLogicExpression>`
2332 * :class:`Shift left logic expression <pyVHDLModel.Expression.ShiftLeftLogicExpression>`
2333 """
2334 pass
2337@export
2338@abstractclass
2339class ShiftArithmeticExpression(ShiftExpression):
2340 """
2341 Represents the base-class of the arithmetic shift expressions ``sra`` and ``sla``.
2343 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2345 .. seealso::
2347 * :class:`Shift right arithmetic expression <pyVHDLModel.Expression.ShiftRightArithmeticExpression>`
2348 * :class:`Shift left arithmetic expression <pyVHDLModel.Expression.ShiftLeftArithmeticExpression>`
2349 """
2350 pass
2353@export
2354@abstractclass
2355class RotateExpression(ShiftExpression):
2356 """
2357 Represents the base-class of the rotate expressions ``ror`` and ``rol``.
2359 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2361 .. seealso::
2363 * :class:`Rotate right expression <pyVHDLModel.Expression.RotateRightExpression>`
2364 * :class:`Rotate left expression <pyVHDLModel.Expression.RotateLeftExpression>`
2365 """
2366 pass
2369@export
2370class ShiftRightLogicExpression(ShiftLogicExpression):
2371 """
2372 Represents a logical right shift expression (``srl``).
2374 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2376 .. admonition:: Example
2378 .. code-block:: VHDL
2380 res := lhs srl rhs;
2381 -- ^^^^^^^^^^^ <- the expression
2382 -- ^^^ <- LeftOperand
2383 -- ^^^ <- RightOperand
2384 """
2385 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " srl ", "") #: The operator's string fragments.
2386 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Srl #: The operator's reserved word.
2389@export
2390class ShiftLeftLogicExpression(ShiftLogicExpression):
2391 """
2392 Represents a logical left shift expression (``sll``).
2394 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2396 .. admonition:: Example
2398 .. code-block:: VHDL
2400 res := lhs sll rhs;
2401 -- ^^^^^^^^^^^ <- the expression
2402 -- ^^^ <- LeftOperand
2403 -- ^^^ <- RightOperand
2404 """
2405 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " sll ", "") #: The operator's string fragments.
2406 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Sll #: The operator's reserved word.
2409@export
2410class ShiftRightArithmeticExpression(ShiftArithmeticExpression):
2411 """
2412 Represents an arithmetic right shift expression (``sra``).
2414 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2416 .. admonition:: Example
2418 .. code-block:: VHDL
2420 res := lhs sra rhs;
2421 -- ^^^^^^^^^^^ <- the expression
2422 -- ^^^ <- LeftOperand
2423 -- ^^^ <- RightOperand
2424 """
2425 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " sra ", "") #: The operator's string fragments.
2426 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Sra #: The operator's reserved word.
2429@export
2430class ShiftLeftArithmeticExpression(ShiftArithmeticExpression):
2431 """
2432 Represents an arithmetic left shift expression (``sla``).
2434 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2436 .. admonition:: Example
2438 .. code-block:: VHDL
2440 res := lhs sla rhs;
2441 -- ^^^^^^^^^^^ <- the expression
2442 -- ^^^ <- LeftOperand
2443 -- ^^^ <- RightOperand
2444 """
2445 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " sla ", "") #: The operator's string fragments.
2446 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Sla #: The operator's reserved word.
2449@export
2450class RotateRightExpression(RotateExpression):
2451 """
2452 Represents a right rotate expression (``ror``).
2454 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2456 .. admonition:: Example
2458 .. code-block:: VHDL
2460 res := lhs ror rhs;
2461 -- ^^^^^^^^^^^ <- the expression
2462 -- ^^^ <- LeftOperand
2463 -- ^^^ <- RightOperand
2464 """
2465 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " ror ", "") #: The operator's string fragments.
2466 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Ror #: The operator's reserved word.
2469@export
2470class RotateLeftExpression(RotateExpression):
2471 """
2472 Represents a left rotate expression (``rol``).
2474 Both operands are available as :data:`LeftOperand` and :data:`RightOperand`.
2476 .. admonition:: Example
2478 .. code-block:: VHDL
2480 res := lhs rol rhs;
2481 -- ^^^^^^^^^^^ <- the expression
2482 -- ^^^ <- LeftOperand
2483 -- ^^^ <- RightOperand
2484 """
2485 _FORMAT: ClassVar[tuple[str, str, str]] = ("", " rol ", "") #: The operator's string fragments.
2486 _RESERVED_WORD: ClassVar[ReservedWord] = ReservedWord.Rol #: The operator's reserved word.
2489@export
2490class QualifiedExpression(BaseExpression, ParenthesisExpression):
2491 """
2492 Represents a qualified expression.
2494 A qualified expression states the subtype (:data:`Subtype`) of its operand (:data:`Operand`),
2495 resolving which of several overloaded meanings is intended.
2497 .. admonition:: Example
2499 .. code-block:: VHDL
2501 res := byte'(others => '0');
2502 -- ^^^^ <- Subtype
2503 -- ^^^^^^^^^^^^^^^ <- Operand
2504 """
2505 _operand: ExpressionUnion #: The expression being qualified.
2506 _subtype: Symbol #: Reference to the subtype qualifying the expression.
2508 def __init__(self, subtype: Symbol, operand: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2509 """
2510 Initializes a qualified expression.
2512 :param subtype: Reference to the subtype qualifying the expression.
2513 :param operand: The expression being qualified.
2514 :param parent: The parent model entity of this entity.
2515 """
2516 super().__init__(parent)
2518 self._operand = operand
2519 operand.Parent = self
2521 self._subtype = subtype
2522 subtype.Parent = self
2524 @readonly
2525 def Operand(self) -> ExpressionUnion:
2526 """
2527 Read-only property to access the operand (:attr:`_operand`).
2529 :returns: The operand.
2530 """
2531 return self._operand
2533 @readonly
2534 def Subtype(self) -> Symbol:
2535 """
2536 Read-only property to access the subtype (:attr:`_subtype`).
2538 :returns: The subtype.
2539 """
2540 return self._subtype
2542 def Copy(self) -> Self:
2543 """
2544 Create a copy of this qualified expression.
2546 The copy has no parent. Its subtype and operand are copies of this expression's subtype and operand.
2548 :returns: The new qualified expression.
2549 """
2550 return self.__class__(self._subtype.Copy(), self._operand.Copy())
2552 def Visit(self, visitor: Visitor) -> None:
2553 """
2554 Walk this qualified expression, its subtype and its operand with a visitor.
2556 :param visitor: The visitor receiving the events.
2557 """
2558 visitor.VisitQualifiedExpression(self)
2559 self._subtype.Visit(visitor)
2560 visitor.VisitApostrophe(self)
2561 self._operand.Visit(visitor)
2562 visitor.DepartQualifiedExpression(self)
2564 def __str__(self) -> str:
2565 """
2566 Formats the qualified expression.
2568 **Format:** ``byte'(val)``
2570 :returns: Formatted qualified expression.
2571 """
2572 return f"{self._subtype}'({self._operand!s})"
2575@export
2576@abstractclass
2577class TernaryExpression(BaseExpression):
2578 """
2579 Represents the base-class of all ternary expressions.
2581 .. seealso::
2583 * :class:`When else expression <pyVHDLModel.Expression.WhenElseExpression>`
2584 """
2586 _PRECEDENCE: ClassVar[OperatorPrecedence] #: The operator's precedence level.
2587 _FORMAT: ClassVar[tuple[str, str, str, str]] #: The operator's string representation as four fragments.
2588 _firstOperand: ExpressionUnion #: The operator's first operand.
2589 _secondOperand: ExpressionUnion #: The operator's second operand.
2590 _thirdOperand: ExpressionUnion #: The operator's third operand.
2592 def __init__(
2593 self,
2594 firstOperand: ExpressionUnion,
2595 secondOperand: ExpressionUnion,
2596 thirdOperand: ExpressionUnion,
2597 parent: Nullable[ModelEntity] = None
2598 ) -> None:
2599 """
2600 Initializes a ternary expression.
2602 :param firstOperand: The operator's first operand.
2603 :param secondOperand: The operator's second operand.
2604 :param thirdOperand: The operator's third operand.
2605 :param parent: The parent model entity of this entity.
2606 """
2607 super().__init__(parent)
2609 self._firstOperand = firstOperand
2610 firstOperand.Parent = self
2612 self._secondOperand = secondOperand
2613 secondOperand.Parent = self
2615 self._thirdOperand = thirdOperand
2616 thirdOperand.Parent = self
2618 def __str__(self) -> str:
2619 """
2620 Formats the ternary expression.
2622 **Format:** ``val when cond else other``
2624 :returns: Formatted ternary expression.
2625 """
2626 return "{beforeFirstOperator}{firstOperand!s}{beforeSecondOperator}{secondOperand!s}{beforeThirdOperator}{thirdOperand!s}{lastOperator}".format(
2627 beforeFirstOperator=self._FORMAT[0],
2628 firstOperand=self._firstOperand,
2629 beforeSecondOperator=self._FORMAT[1],
2630 secondOperand=self._secondOperand,
2631 beforeThirdOperator=self._FORMAT[2],
2632 thirdOperand=self._thirdOperand,
2633 lastOperator=self._FORMAT[3],
2634 )
2637@export
2638class WhenElseExpression(TernaryExpression):
2639 """
2640 Represents a conditional expression.
2642 A conditional expression selects between two values (:data:`ThenValue`, :data:`ElseValue`) based on
2643 a condition (:data:`Condition`). It is usable anywhere an expression is expected - distinct from
2644 :class:`~pyVHDLModel.Common.ConditionalExpression`, which models the cascading ``when``/``else``
2645 list of a conditional *assignment*.
2647 .. admonition:: Example
2649 .. code-block:: VHDL
2651 res := a when f else b;
2652 -- ^ <- ThenValue
2653 -- ^ <- Condition
2654 -- ^ <- ElseValue
2655 """
2656 _PRECEDENCE: ClassVar[OperatorPrecedence] = OperatorPrecedence.Conditional #: The operator's precedence level.
2657 _FORMAT: ClassVar[tuple[str, str, str, str]] = ("", " when ", " else ", "") #: The operator's string fragments.
2659 def __init__(
2660 self,
2661 thenValue: ExpressionUnion,
2662 condition: ExpressionUnion,
2663 elseValue: ExpressionUnion,
2664 parent: Nullable[ModelEntity] = None
2665 ) -> None:
2666 """
2667 Initializes a conditional expression.
2669 :param thenValue: The value if the condition holds.
2670 :param condition: The condition selecting between both values.
2671 :param elseValue: The value if the condition does not hold.
2672 :param parent: The parent model entity of this entity.
2673 """
2674 super().__init__(thenValue, condition, elseValue, parent)
2676 @readonly
2677 def ThenValue(self) -> ExpressionUnion:
2678 """
2679 Read-only property to access the then value (:attr:`_firstOperand`).
2681 :returns: The then value.
2682 """
2683 return self._firstOperand
2685 @readonly
2686 def Condition(self) -> ExpressionUnion:
2687 """
2688 Read-only property to access the condition (:attr:`_secondOperand`).
2690 :returns: The condition.
2691 """
2692 return self._secondOperand
2694 @readonly
2695 def ElseValue(self) -> ExpressionUnion:
2696 """
2697 Read-only property to access the else value (:attr:`_thirdOperand`).
2699 :returns: The else value.
2700 """
2701 return self._thirdOperand
2703 def Copy(self) -> Self:
2704 """
2705 Create a copy of this conditional expression.
2707 The copy has no parent. Its values and condition are copies of this expression's values and condition.
2709 :returns: The new conditional expression.
2710 """
2711 return self.__class__(self._firstOperand.Copy(), self._secondOperand.Copy(), self._thirdOperand.Copy())
2713 def Visit(self, visitor: Visitor) -> None:
2714 """
2715 Walk this conditional expression, its value, condition and alternative value with a visitor.
2717 :param visitor: The visitor receiving the events.
2718 """
2719 visitor.VisitWhenElseExpression(self)
2720 self._firstOperand.Visit(visitor)
2721 visitor.VisitWhen(self)
2722 self._secondOperand.Visit(visitor)
2723 visitor.VisitElse(self)
2724 self._thirdOperand.Visit(visitor)
2725 visitor.DepartWhenElseExpression(self)
2728@export
2729class FunctionCall(BaseExpression):
2730 """
2731 Represents a call to a function.
2733 .. admonition:: Example
2735 .. code-block:: VHDL
2737 res := maximum(a, b);
2738 -- ^^^^^^^^^^^^^ <- the call
2739 """
2740 def Copy(self) -> Self:
2741 """
2742 Create a copy of this function call.
2744 The copy has no parent.
2746 :returns: The new function call.
2747 """
2748 return self.__class__()
2751@export
2752@abstractclass
2753class Allocation(BaseExpression):
2754 """
2755 Represents the base-class of all allocations via ``new``.
2757 .. seealso::
2759 * :class:`Subtype allocation <pyVHDLModel.Expression.SubtypeAllocation>`
2760 * :class:`Qualified expression allocation <pyVHDLModel.Expression.QualifiedExpressionAllocation>`
2761 """
2762 pass
2765@export
2766class SubtypeAllocation(Allocation):
2767 """
2768 Represents an allocation of a subtype via ``new``.
2770 The allocated subtype is available as :data:`Subtype`. The allocated object is default-initialized.
2772 .. admonition:: Example
2774 .. code-block:: VHDL
2776 p := new integer;
2777 -- ^^^^^^^ <- Subtype
2778 """
2779 _subtype: Symbol #: Reference to the subtype being allocated.
2781 def __init__(self, subtype: Symbol, parent: Nullable[ModelEntity] = None) -> None:
2782 """
2783 Initializes an allocation of a subtype via ``new``.
2785 :param subtype: Reference to the subtype being allocated.
2786 :param parent: The parent model entity of this entity.
2787 """
2788 super().__init__(parent)
2790 self._subtype = subtype
2791 subtype.Parent = self
2793 @readonly
2794 def Subtype(self) -> Symbol:
2795 """
2796 Read-only property to access the subtype (:attr:`_subtype`).
2798 :returns: The subtype.
2799 """
2800 return self._subtype
2802 def Copy(self) -> Self:
2803 """
2804 Create a copy of this subtype allocation.
2806 The copy has no parent. Its subtype is a copy of this allocation's subtype.
2808 :returns: The new subtype allocation.
2809 """
2810 return self.__class__(self._subtype.Copy())
2812 def Visit(self, visitor: Visitor) -> None:
2813 """
2814 Walk this allocation and its subtype with a visitor.
2816 :param visitor: The visitor receiving the events.
2817 """
2818 visitor.VisitSubtypeAllocation(self)
2819 self._subtype.Visit(visitor)
2820 visitor.DepartSubtypeAllocation(self)
2822 def __str__(self) -> str:
2823 """
2824 Formats the subtype allocation.
2826 **Format:** ``new node``
2828 :returns: Formatted subtype allocation.
2829 """
2830 return f"new {self._subtype!s}"
2833@export
2834class QualifiedExpressionAllocation(Allocation):
2835 """
2836 Represents an allocation initialized by a qualified expression.
2838 The qualified expression providing the initial value is available as :data:`QualifiedExpression`.
2840 .. admonition:: Example
2842 .. code-block:: VHDL
2844 p := new integer'(5);
2845 -- ^^^^^^^^^^^ <- QualifiedExpression
2846 """
2847 _qualifiedExpression: QualifiedExpression #: The qualified expression the allocated object is initialized with.
2849 def __init__(self, qualifiedExpression: QualifiedExpression, parent: Nullable[ModelEntity] = None) -> None:
2850 """
2851 Initializes an allocation initialized by a qualified expression.
2853 :param qualifiedExpression: The qualified expression the allocated object is initialized with.
2854 :param parent: The parent model entity of this entity.
2855 """
2856 super().__init__(parent)
2858 self._qualifiedExpression = qualifiedExpression
2859 qualifiedExpression.Parent = self
2861 @readonly
2862 def QualifiedExpression(self) -> QualifiedExpression:
2863 """
2864 Read-only property to access the qualified expression (:attr:`_qualifiedExpression`).
2866 :returns: The qualified expression.
2867 """
2868 return self._qualifiedExpression
2870 def Copy(self) -> Self:
2871 """
2872 Create a copy of this qualified expression allocation.
2874 The copy has no parent. Its qualified expression is a copy of this allocation's qualified expression.
2876 :returns: The new qualified expression allocation.
2877 """
2878 return self.__class__(self._qualifiedExpression.Copy())
2880 def Visit(self, visitor: Visitor) -> None:
2881 """
2882 Walk this allocation and its qualified expression with a visitor.
2884 :param visitor: The visitor receiving the events.
2885 """
2886 visitor.VisitQualifiedExpressionAllocation(self)
2887 self._qualifiedExpression.Visit(visitor)
2888 visitor.DepartQualifiedExpressionAllocation(self)
2890 def __str__(self) -> str:
2891 """
2892 Formats the qualified expression allocation.
2894 **Format:** ``new byte'(val)``
2896 :returns: Formatted qualified expression allocation.
2897 """
2898 return f"new {self._qualifiedExpression!s}"
2901@export
2902@abstractclass
2903class AggregateElement(ModelEntity):
2904 """
2905 Represents the base-class of all aggregate elements.
2907 Every element carries the value assigned to it (:data:`Expression`).
2909 .. seealso::
2911 * :class:`Simple aggregate element <pyVHDLModel.Expression.SimpleAggregateElement>`
2912 * :class:`Indexed aggregate element <pyVHDLModel.Expression.IndexedAggregateElement>`
2913 * :class:`Ranged aggregate element <pyVHDLModel.Expression.RangedAggregateElement>`
2914 * :class:`Named aggregate element <pyVHDLModel.Expression.NamedAggregateElement>`
2915 * :class:`Others aggregate element <pyVHDLModel.Expression.OthersAggregateElement>`
2916 """
2918 _expression: ExpressionUnion #: The expression this aggregate element supplies.
2920 def __init__(self, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
2921 """
2922 Initializes an aggregate element.
2924 :param expression: The expression this aggregate element supplies.
2925 :param parent: The parent model entity of this entity.
2926 """
2927 super().__init__(parent)
2929 self._expression = expression
2930 expression.Parent = self
2932 @readonly
2933 def Expression(self) -> ExpressionUnion:
2934 """
2935 Read-only property to access the expression (:attr:`_expression`).
2937 :returns: The expression.
2938 """
2939 return self._expression
2941 def Copy(self) -> Self:
2942 """
2943 Create a copy of this aggregate element.
2945 The copy has no parent. Its expression is a copy of this element's expression.
2947 :returns: The new aggregate element.
2948 """
2949 return self.__class__(self._expression.Copy())
2952@export
2953class SimpleAggregateElement(AggregateElement):
2954 """
2955 Represents an aggregate element given by position.
2957 A positional element has no choice of its own; only its value (:data:`Expression`).
2959 .. admonition:: Example
2961 .. code-block:: VHDL
2963 res := ('1', '0', '1', '0', '1', '0', '1', '0');
2964 -- ^^^ <- Expression
2965 """
2966 def Visit(self, visitor: Visitor) -> None:
2967 """
2968 Walk this positional aggregate element and its expression with a visitor.
2970 :param visitor: The visitor receiving the events.
2971 """
2972 visitor.VisitSimpleAggregateElement(self)
2973 self._expression.Visit(visitor)
2974 visitor.DepartSimpleAggregateElement(self)
2976 def __str__(self) -> str:
2977 """
2978 Formats the simple aggregate element.
2980 **Format:** ``val``
2982 :returns: Formatted simple aggregate element.
2983 """
2984 return str(self._expression)
2987@export
2988class IndexedAggregateElement(AggregateElement):
2989 """
2990 Represents an aggregate element chosen by an index.
2992 The index is available as :data:`Index`, the assigned value as :data:`Expression`.
2994 .. admonition:: Example
2996 .. code-block:: VHDL
2998 res := (0 => '1', others => '0');
2999 -- ^ <- Index
3000 -- ^^^ <- Expression
3001 """
3002 _index: ExpressionUnion #: The index expression selecting the element this value is assigned to.
3004 def __init__(self, index: ExpressionUnion, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
3005 """
3006 Initializes an aggregate element chosen by an index.
3008 :param index: The index expression selecting the element this value is assigned to.
3009 :param expression: The expression this aggregate element supplies.
3010 :param parent: The parent model entity of this entity.
3011 """
3012 super().__init__(expression, parent)
3014 self._index = index
3016 @readonly
3017 def Index(self) -> ExpressionUnion:
3018 """
3019 Read-only property to access the index expression (:attr:`_index`).
3021 :returns: The index expression.
3022 """
3023 return self._index
3025 def Copy(self) -> Self:
3026 """
3027 Create a copy of this indexed aggregate element.
3029 The copy has no parent. Its index and expression are copies of this element's index and expression.
3031 :returns: The new indexed aggregate element.
3032 """
3033 return self.__class__(self._index.Copy(), self._expression.Copy())
3035 def Visit(self, visitor: Visitor) -> None:
3036 """
3037 Walk this aggregate element, its index and its expression with a visitor.
3039 :param visitor: The visitor receiving the events.
3040 """
3041 visitor.VisitIndexedAggregateElement(self)
3042 self._index.Visit(visitor)
3043 visitor.VisitArrow(self)
3044 self._expression.Visit(visitor)
3045 visitor.DepartIndexedAggregateElement(self)
3047 def __str__(self) -> str:
3048 """
3049 Formats the indexed aggregate element.
3051 **Format:** ``0 => val``
3053 :returns: Formatted indexed aggregate element.
3054 """
3055 return f"{self._index!s} => {self._expression!s}"
3058@export
3059class RangedAggregateElement(AggregateElement):
3060 """
3061 Represents an aggregate element chosen by a range.
3063 The range is available as :data:`Range`, the assigned value as :data:`Expression`.
3065 .. admonition:: Example
3067 .. code-block:: VHDL
3069 res := (1 to 3 => '0', others => '1');
3070 -- ^^^^^^ <- Range
3071 -- ^^^ <- Expression
3072 """
3073 _range: Range #: The range selecting the elements this value is assigned to.
3075 def __init__(self, rng: Range, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
3076 """
3077 Initializes an aggregate element chosen by a range.
3079 :param rng: The range selecting the elements this value is assigned to.
3080 :param expression: The expression this aggregate element supplies.
3081 :param parent: The parent model entity of this entity.
3082 """
3083 super().__init__(expression, parent)
3085 self._range = rng
3086 rng.Parent = self
3088 @readonly
3089 def Range(self) -> Range:
3090 """
3091 Read-only property to access the range (:attr:`_range`).
3093 :returns: The range.
3094 """
3095 return self._range
3097 def Copy(self) -> Self:
3098 """
3099 Create a copy of this ranged aggregate element.
3101 The copy has no parent. Its range and expression are copies of this element's range and expression.
3103 :returns: The new ranged aggregate element.
3104 """
3105 return self.__class__(self._range.Copy(), self._expression.Copy())
3107 def Visit(self, visitor: Visitor) -> None:
3108 """
3109 Walk this aggregate element, its range and its expression with a visitor.
3111 :param visitor: The visitor receiving the events.
3112 """
3113 visitor.VisitRangedAggregateElement(self)
3114 self._range.Visit(visitor)
3115 visitor.VisitArrow(self)
3116 self._expression.Visit(visitor)
3117 visitor.DepartRangedAggregateElement(self)
3119 def __str__(self) -> str:
3120 """
3121 Formats the ranged aggregate element.
3123 **Format:** ``0 to 3 => val``
3125 :returns: Formatted ranged aggregate element.
3126 """
3127 return f"{self._range!s} => {self._expression!s}"
3130@export
3131class NamedAggregateElement(AggregateElement):
3132 """
3133 Represents an aggregate element chosen by a name.
3135 Used for record aggregates, where the choice names a record element (:data:`Name`).
3137 .. admonition:: Example
3139 .. code-block:: VHDL
3141 r := (a => '1', b => '0');
3142 -- ^ <- Name
3143 -- ^^^ <- Expression
3144 """
3145 _name: Symbol #: Reference to the name selecting the element this value is assigned to.
3147 def __init__(self, name: Symbol, expression: ExpressionUnion, parent: Nullable[ModelEntity] = None) -> None:
3148 """
3149 Initializes an aggregate element chosen by a name.
3151 :param name: Reference to the name selecting the element this value is assigned to.
3152 :param expression: The expression this aggregate element supplies.
3153 :param parent: The parent model entity of this entity.
3154 """
3155 super().__init__(expression, parent)
3157 self._name = name
3158 name.Parent = self
3160 @readonly
3161 def Name(self) -> Symbol:
3162 """
3163 Read-only property to access the name (:attr:`_name`).
3165 :returns: The name.
3166 """
3167 return self._name
3169 def Copy(self) -> Self:
3170 """
3171 Create a copy of this named aggregate element.
3173 The copy has no parent. Its name and expression are copies of this element's name and expression.
3175 :returns: The new named aggregate element.
3176 """
3177 return self.__class__(self._name.Copy(), self._expression.Copy())
3179 def Visit(self, visitor: Visitor) -> None:
3180 """
3181 Walk this aggregate element, its name and its expression with a visitor.
3183 :param visitor: The visitor receiving the events.
3184 """
3185 visitor.VisitNamedAggregateElement(self)
3186 self._name.Visit(visitor)
3187 visitor.VisitArrow(self)
3188 self._expression.Visit(visitor)
3189 visitor.DepartNamedAggregateElement(self)
3191 def __str__(self) -> str:
3192 """
3193 Formats the named aggregate element.
3195 **Format:** ``elem => val``
3197 :returns: Formatted named aggregate element.
3198 """
3199 return "{name!s} => {value!s}".format(
3200 name=self._name,
3201 value=self._expression,
3202 )
3205@export
3206class OthersAggregateElement(AggregateElement):
3207 """
3208 Represents the ``others`` element of an aggregate.
3210 It supplies the value (:data:`Expression`) for every choice not named explicitly.
3212 .. admonition:: Example
3214 .. code-block:: VHDL
3216 res := (0 => '1', others => '0');
3217 -- ^^^^^^ <- the choice
3218 -- ^^^ <- Expression
3219 """
3220 def Visit(self, visitor: Visitor) -> None:
3221 """
3222 Walk this ``others`` aggregate element and its expression with a visitor.
3224 :param visitor: The visitor receiving the events.
3225 """
3226 visitor.VisitOthersAggregateElement(self)
3227 self._expression.Visit(visitor)
3228 visitor.DepartOthersAggregateElement(self)
3230 def __str__(self) -> str:
3231 """
3232 Formats the ``others`` aggregate element.
3234 **Format:** ``others => val``
3236 :returns: Formatted ``others`` aggregate element.
3237 """
3238 return "others => {value!s}".format(
3239 value=self._expression,
3240 )
3243@export
3244class Aggregate(BaseExpression):
3245 """
3246 Represents an aggregate.
3248 An aggregate composes a value from its elements (:data:`Elements`), each of which associates a
3249 choice with a value.
3251 .. admonition:: Example
3253 .. code-block:: VHDL
3255 res := (0 => '1', 1 to 3 => '0', others => '1');
3256 -- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ <- Elements
3257 """
3258 _elements: list[AggregateElement] #: List of all elements of this aggregate, in the order they were written.
3260 def __init__(self, elements: Iterable[AggregateElement], parent: Nullable[ModelEntity] = None) -> None:
3261 """
3262 Initializes an aggregate.
3264 :param elements: List of all elements of this aggregate, in the order they were written.
3265 :param parent: The parent model entity of this entity.
3266 """
3267 super().__init__(parent)
3269 self._elements = elementList = []
3270 for element in elements:
3271 elementList.append(element)
3272 element.Parent = self
3274 @readonly
3275 def Elements(self) -> list[AggregateElement]:
3276 """
3277 Read-only property to access the elements (:attr:`_elements`).
3279 :returns: List of elements.
3280 """
3281 return self._elements
3283 def Copy(self) -> Self:
3284 """
3285 Create a copy of this aggregate.
3287 The copy has no parent. Its elements are copies of this aggregate's elements.
3289 :returns: The new aggregate.
3290 """
3291 return self.__class__([element.Copy() for element in self._elements])
3293 def Visit(self, visitor: Visitor) -> None:
3294 """
3295 Walk this aggregate and its elements with a visitor.
3297 :param visitor: The visitor receiving the events.
3298 """
3299 visitor.VisitAggregate(self)
3300 for position, element in enumerate(self._elements):
3301 if position > 0:
3302 visitor.VisitComma(self)
3304 element.Visit(visitor)
3306 visitor.DepartAggregate(self)
3308 def __str__(self) -> str:
3309 """
3310 Formats the aggregate.
3312 **Format:** ``(1, others => 0)``
3314 :returns: Formatted aggregate.
3315 """
3316 choices = [str(element) for element in self._elements]
3317 return "({choices})".format(
3318 choices=", ".join(choices)
3319 )