PoC.fifo.shift

This FIFO implementation is based on an internal shift register. This is especially useful for smaller FIFO sizes, which can be implemented in LUT storage on some devices (e.g. Xilinx’ SRLs). Only a single read pointer is maintained, which determines the number of valid entries within the underlying shift register.

The specified depth (MIN_DEPTH) is rounded up to the next suitable value.

Entity Declaration:

 1entity fifo_shift is
 2  generic (
 3    D_BITS    : positive;               -- Data Width
 4    MIN_DEPTH : positive                -- Minimum FIFO Size in Words
 5  );
 6  port (
 7    -- Global Control
 8    clk  : in  std_logic;
 9    rst  : in  std_logic;
10    fill : out std_logic_vector(log2ceilnz(MIN_DEPTH) downto 0); -- Fill'left = Empty, Fill'left = no vld
11                                                                 -- If vld='1' then fill(fill'left -1 downto 0) +1 is the number of Words saved
12
13    -- Writing Interface
14    put  : in  std_logic;                            -- Write Request
15    din  : in  std_logic_vector(D_BITS-1 downto 0);  -- Input Data
16    ful  : out std_logic;                            -- Capacity Exhausted
17
18    -- Reading Interface
19    got  : in  std_logic;                            -- Read Done Strobe