PoC.fifo.Stage

Its primary use is the decoupling of enable domains in a processing pipeline. Data storage is limited to two words only so as to allow both the ful and the vld indicators to be driven by registers.

Entity Declaration:

 1use IEEE.std_logic_1164.all;
 2
 3entity fifo_Stage is
 4  generic (
 5    D_BITS       : positive;
 6    STAGES       : natural := 1;    -- 0 creates a passthrough, all values above creates one pipeline stage of the set depth
 7    LIGHT_WEIGHT : boolean := FALSE -- This option uses half of registers but oszilates between full and empty! Use only when restriction is acceptable (e.g. for Address channel in AXI)
 8  );
 9  port (
10    -- Control
11    clk : in std_logic; -- Clock
12    rst : in std_logic; -- Synchronous Reset
13
14    -- Input
15    put : in std_logic;                             -- Put Value
16    di  : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input
17    ful : out std_logic;                            -- Full
18
19    -- Output
20    vld : out std_logic;                             -- Data Available