Coverage for pyVHDLModel / Regions.py: 51%
102 statements
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1# ==================================================================================================================== #
2# __ ___ _ ____ _ __ __ _ _ #
3# _ __ _ \ \ / / | | | _ \| | | \/ | ___ __| | ___| | #
4# | '_ \| | | \ \ / /| |_| | | | | | | |\/| |/ _ \ / _` |/ _ \ | #
5# | |_) | |_| |\ V / | _ | |_| | |___| | | | (_) | (_| | __/ | #
6# | .__/ \__, | \_/ |_| |_|____/|_____|_| |_|\___/ \__,_|\___|_| #
7# |_| |___/ #
8# ==================================================================================================================== #
9# Authors: #
10# Patrick Lehmann #
11# #
12# License: #
13# ==================================================================================================================== #
14# Copyright 2017-2025 Patrick Lehmann - Boetzingen, Germany #
15# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany #
16# #
17# Licensed under the Apache License, Version 2.0 (the "License"); #
18# you may not use this file except in compliance with the License. #
19# You may obtain a copy of the License at #
20# #
21# http://www.apache.org/licenses/LICENSE-2.0 #
22# #
23# Unless required by applicable law or agreed to in writing, software #
24# distributed under the License is distributed on an "AS IS" BASIS, #
25# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
26# See the License for the specific language governing permissions and #
27# limitations under the License. #
28# #
29# SPDX-License-Identifier: Apache-2.0 #
30# ==================================================================================================================== #
31#
32"""
33This module contains parts of an abstract document language model for VHDL.
35tbd.
36"""
37from typing import List, Dict, Iterable, Optional as Nullable, Any
39from pyTooling.Decorators import export, readonly
40from pyTooling.MetaClasses import ExtendedType
42from pyVHDLModel.Object import Constant, SharedVariable, File, Variable, Signal
43from pyVHDLModel.Subprogram import Subprogram, Function, Procedure
44from pyVHDLModel.Type import Subtype, FullType
47@export
48class ConcurrentDeclarationRegionMixin(metaclass=ExtendedType, mixin=True):
49 # FIXME: define list prefix type e.g. via Union
50 _declaredItems: List #: List of all declared items in this concurrent declaration region.
52 # _attributes: Dict[str, Attribute]
53 # _aliases: Dict[str, Alias]
54 _types: Dict[str, FullType] #: Dictionary of all types declared in this concurrent declaration region.
55 _subtypes: Dict[str, Subtype] #: Dictionary of all subtypes declared in this concurrent declaration region.
56 # _objects: Dict[str, Union[Constant, Variable, Signal]]
57 _constants: Dict[str, Constant] #: Dictionary of all constants declared in this concurrent declaration region.
58 _signals: Dict[str, Signal] #: Dictionary of all signals declared in this concurrent declaration region.
59 _sharedVariables: Dict[str, SharedVariable] #: Dictionary of all shared variables declared in this concurrent declaration region.
60 _files: Dict[str, File] #: Dictionary of all files declared in this concurrent declaration region.
61 # _subprograms: Dict[str, Dict[str, Subprogram]] #: Dictionary of all subprograms declared in this concurrent declaration region.
62 _functions: Dict[str, Dict[str, Function]] #: Dictionary of all functions declared in this concurrent declaration region.
63 _procedures: Dict[str, Dict[str, Procedure]] #: Dictionary of all procedures declared in this concurrent declaration region.
64 _components: Dict[str, Any] #: Dictionary of all components declared in this concurrent declaration region.
66 def __init__(self, declaredItems: Nullable[Iterable] = None) -> None:
67 # TODO: extract to mixin
68 self._declaredItems = [] # TODO: convert to dict
69 if declaredItems is not None: 69 ↛ 70line 69 didn't jump to line 70 because the condition on line 69 was never true
70 for item in declaredItems:
71 self._declaredItems.append(item)
72 item._parent = self
74 self._types = {}
75 self._subtypes = {}
76 # self._objects = {}
77 self._constants = {}
78 self._signals = {}
79 self._sharedVariables = {}
80 self._files = {}
81 # self._subprograms = {}
82 self._functions = {}
83 self._procedures = {}
84 self._components = {}
86 @readonly
87 def DeclaredItems(self) -> List:
88 return self._declaredItems
90 @readonly
91 def Types(self) -> Dict[str, FullType]:
92 return self._types
94 @readonly
95 def Subtypes(self) -> Dict[str, Subtype]:
96 return self._subtypes
98 # @readonly
99 # def Objects(self) -> Dict[str, Union[Constant, SharedVariable, Signal, File]]:
100 # return self._objects
102 @readonly
103 def Constants(self) -> Dict[str, Constant]:
104 return self._constants
106 @readonly
107 def Signals(self) -> Dict[str, Signal]:
108 return self._signals
110 @readonly
111 def SharedVariables(self) -> Dict[str, SharedVariable]:
112 return self._sharedVariables
114 @readonly
115 def Files(self) -> Dict[str, File]:
116 return self._files
118 # @readonly
119 # def Subprograms(self) -> Dict[str, Subprogram]:
120 # return self._subprograms
122 @readonly
123 def Functions(self) -> Dict[str, Dict[str, Function]]:
124 return self._functions
126 @readonly
127 def Procedures(self) -> Dict[str, Dict[str, Procedure]]:
128 return self._procedures
130 @readonly
131 def Components(self) -> Dict[str, Any]:
132 return self._components
134 def IndexDeclaredItems(self) -> None:
135 """
136 Index declared items listed in the concurrent declaration region.
138 .. rubric:: Algorithm
140 1. Iterate all declared items:
142 * Every declared item is added to :attr:`_namespace`.
143 * If the declared item is a :class:`~pyVHDLModel.Type.FullType`, then add an entry to :attr:`_types`.
144 * If the declared item is a :class:`~pyVHDLModel.Type.SubType`, then add an entry to :attr:`_subtypes`.
145 * If the declared item is a :class:`~pyVHDLModel.Subprogram.Function`, then add an entry to :attr:`_functions`.
146 * If the declared item is a :class:`~pyVHDLModel.Subprogram.Procedure`, then add an entry to :attr:`_procedures`.
147 * If the declared item is a :class:`~pyVHDLModel.Object.Constant`, then add an entry to :attr:`_constants`.
148 * If the declared item is a :class:`~pyVHDLModel.Object.Signal`, then add an entry to :attr:`_signals`.
149 * If the declared item is a :class:`~pyVHDLModel.Object.Variable`, TODO.
150 * If the declared item is a :class:`~pyVHDLModel.Object.SharedVariable`, then add an entry to :attr:`_sharedVariables`.
151 * If the declared item is a :class:`~pyVHDLModel.Object.File`, then add an entry to :attr:`_files`.
152 * If the declared item is neither of these types, call :meth:`_IndexOtherDeclaredItem`. |br|
153 Derived classes may override this virtual function.
155 .. seealso::
157 :meth:`pyVHDLModel.Design.IndexPackages`
158 Iterate all packages in the design and index declared items.
159 :meth:`pyVHDLModel.Library.IndexPackages`
160 Iterate all packages in the library and index declared items.
161 :meth:`pyVHDLModel.Library._IndexOtherDeclaredItem`
162 Iterate all packages in the library and index declared items.
163 """
164 from pyVHDLModel.DesignUnit import Component
166 for item in self._declaredItems:
167 if isinstance(item, FullType):
168 self._types[item._normalizedIdentifier] = item
169 self._namespace._elements[item._normalizedIdentifier] = item
170 elif isinstance(item, Subtype): 170 ↛ 173line 170 didn't jump to line 173 because the condition on line 170 was always true
171 self._subtypes[item._normalizedIdentifier] = item
172 self._namespace._elements[item._normalizedIdentifier] = item
173 elif isinstance(item, Function):
174 self._functions[item._normalizedIdentifier] = item
175 self._namespace._elements[item._normalizedIdentifier] = item
176 elif isinstance(item, Procedure):
177 self._procedures[item._normalizedIdentifier] = item
178 self._namespace._elements[item._normalizedIdentifier] = item
179 elif isinstance(item, Constant):
180 for normalizedIdentifier in item._normalizedIdentifiers:
181 self._constants[normalizedIdentifier] = item
182 self._namespace._elements[normalizedIdentifier] = item
183 # self._objects[normalizedIdentifier] = item
184 elif isinstance(item, Signal):
185 for normalizedIdentifier in item._normalizedIdentifiers:
186 self._signals[normalizedIdentifier] = item
187 self._namespace._elements[normalizedIdentifier] = item
188 elif isinstance(item, Variable):
189 print(f"IndexDeclaredItems - {item._identifiers}")
190 elif isinstance(item, SharedVariable):
191 for normalizedIdentifier in item._normalizedIdentifiers:
192 self._sharedVariables[normalizedIdentifier] = item
193 self._namespace._elements[normalizedIdentifier] = item
194 elif isinstance(item, File):
195 for normalizedIdentifier in item._normalizedIdentifiers:
196 self._files[normalizedIdentifier] = item
197 self._namespace._elements[normalizedIdentifier] = item
198 elif isinstance(item, Component):
199 self._components[item._normalizedIdentifier] = item
200 self._namespace._elements[item._normalizedIdentifier] = item
201 else:
202 self._IndexOtherDeclaredItem(item)
204 def _IndexOtherDeclaredItem(self, item) -> None:
205 print(f"_IndexOtherDeclaredItem - {item}\n ({' -> '.join(t.__name__ for t in type(item).mro())})")