VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect @tmeissner
#24 3 0 · 2020/11/30 tmeissner/cryptocores · tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography

Cryptography IP-cores & tests written in VHDL / Verilog.

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.