NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL @umarcor
#36 1 0 · 2022/02/05 stnolting/neorv32 · tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD
OSVVM & UVVM: Differences and Unification @umarcor
#33 0 0 · 2021/10/30 · tags: vhdl, verification, methodology, osvvm, uvvm, unification
Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry @umarcor
#31 0 0 · 2021/10/21 · tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl
Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples
VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect @tmeissner
#24 3 0 · 2020/11/30 tmeissner/cryptocores · tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography
VHDL needs you! @umarcor
#22 2 0 · 2020/11/13 · tags: vhdl, LRM, VASG, LaTeX, GitLab
What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? @umarcor
#19 2 1 · 2020/10/09 · tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin