Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry @umarcor
#31 0 0 · 2021/10/21 · tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl
Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples
Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools @umarcor
#21 3 0 · 2020/10/27 antonblanchard/microwatt · tags: microwatt, ghdl, simulation, synthesis, power, openisa
Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools @umarcor
#21 3 0 · 2020/10/27 antonblanchard/microwatt · tags: microwatt, ghdl, simulation, synthesis, power, openisa
Structured constraint files for HDL designs targeting FPGA boards @umarcor
#20 1 0 · 2020/10/22 hdl/constraints · tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc
What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? @umarcor
#19 2 1 · 2020/10/09 · tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin
Docker dashboard (on Windows and Mac OS) @eine
#18 1 0 · 2020/10/09 ghdl/docker · tags: docker, container, simulation, synthesis, programming
How to convert vhdl to other formats @tmeissner
#17 3 0 · 2020/09/28 · tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl