Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples

Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink.

NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile.