Open Source Verification Bundle (OSVB) @umarcor
#30 0 0 · 2021/10/20 umarcor/osvb · tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys
MINGW-packages for Electronic Design Automation (EDA) @umarcor
#27 1 0 · 2021/01/19 hdl/MINGW-packages · tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD
Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples
VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect @tmeissner
#24 3 0 · 2020/11/30 tmeissner/cryptocores · tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography
Building and deploying container images for open source EDA @eine
#23 2 0 · 2020/11/23 hdl/containers · tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3
How to convert vhdl to other formats @tmeissner
#17 3 0 · 2020/09/28 · tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) @tmeissner
#5 3 0 · 2020/08/18 tmeissner/psl_with_ghdl · tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage