References to elaborated readings such as docs, papers, books, guides, wikis, etc.

OSVVM & UVVM: Differences and Unification @umarcor
#33 0 0 · 2021/10/30 · tags: vhdl, verification, methodology, osvvm, uvvm, unification
Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry @umarcor
#31 0 0 · 2021/10/21 · tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl
Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples
SusanaCanel - Proyectos VHDL @umarcor
#15 1 0 · 2020/09/18 susanacanel/proyectos-vhdl · tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera
Open Source Formal Verification in VHDL @Ahmad-Zaklouta
#13 1 0 · 2020/09/07
Learning FPGA programming, key points for a software developer @eine
#10 1 0 · 2020/09/01 · tags: learning, fpga, programming
What’s new in VHDL-2019 - VHDLwhiz @tmeissner
#9 2 0 · 2020/08/28 · tags: vhdl-2019, ieee, verification, vhdlwhiz
Create your own VVC for UVVM @Ahmad-Zaklouta
#7 1 6 · 2020/08/19 · tags: verification, simulation, uvvm
Addressing VHDL Verification Challenges with OSVVM @tmeissner
#4 4 0 · 2020/08/18 · tags: verification, simulation, osvvm, mentor
What Can GitHub Tell Us About the HDL Industry? @eine
#2 3 0 · 2020/08/18 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit