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NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL @umarcor
#36 1 0 · 2022/02/05 stnolting/neorv32 · tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD
CHIPS Alliance Announces Xilinx as its Newest Member @umarcor
#35 0 0 · 2022/02/05 SymbiFlow/fpga-interchange-schema · tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright
OSVVM & UVVM: Differences and Unification @umarcor
#33 0 0 · 2021/10/30 · tags: vhdl, verification, methodology, osvvm, uvvm, unification
What Can GitHub Tell Us About the HDL Industry? (Part 5) @umarcor
#32 0 0 · 2021/10/27 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson
Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry @umarcor
#31 0 0 · 2021/10/21 · tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl
Open Source Verification Bundle (OSVB) @umarcor
#30 0 0 · 2021/10/20 umarcor/osvb · tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys
MINGW-packages for Electronic Design Automation (EDA) @umarcor
#27 1 0 · 2021/01/19 hdl/MINGW-packages · tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD
Mixed HDL on Fomu, with GHDL and Yosys @umarcor
#26 3 0 · 2020/12/02 im-tomu/fomu-workshop · tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples
VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect @tmeissner
#24 3 0 · 2020/11/30 tmeissner/cryptocores · tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography
Building and deploying container images for open source EDA @eine
#23 2 0 · 2020/11/23 hdl/containers · tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3
VHDL needs you! @umarcor
#22 2 0 · 2020/11/13 · tags: vhdl, LRM, VASG, LaTeX, GitLab
Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools @umarcor
#21 3 0 · 2020/10/27 antonblanchard/microwatt · tags: microwatt, ghdl, simulation, synthesis, power, openisa
Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools @umarcor
#21 3 0 · 2020/10/27 antonblanchard/microwatt · tags: microwatt, ghdl, simulation, synthesis, power, openisa
Structured constraint files for HDL designs targeting FPGA boards @umarcor
#20 1 0 · 2020/10/22 hdl/constraints · tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc
What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? @umarcor
#19 2 1 · 2020/10/09 · tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin
Docker dashboard (on Windows and Mac OS) @eine
#18 1 0 · 2020/10/09 ghdl/docker · tags: docker, container, simulation, synthesis, programming
How to convert vhdl to other formats @tmeissner
#17 3 0 · 2020/09/28 · tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl
Combining VUnit tests with cocotb components @umarcor
#16 2 0 · 2020/09/28 umarcor/vunit-cocotb · tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl
SusanaCanel - Proyectos VHDL @umarcor
#15 1 0 · 2020/09/18 susanacanel/proyectos-vhdl · tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera
What Can GitHub Tell Us About the HDL Industry? (Part 4) @umarcor
#14 1 0 · 2020/09/18 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit
Open Source Formal Verification in VHDL @Ahmad-Zaklouta
#13 1 0 · 2020/09/07
What Can GitHub Tell Us About the HDL Industry? (Part 3) @umarcor
#11 1 0 · 2020/09/02 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit
Learning FPGA programming, key points for a software developer @eine
#10 1 0 · 2020/09/01 · tags: learning, fpga, programming
What’s new in VHDL-2019 - VHDLwhiz @tmeissner
#9 2 0 · 2020/08/28 · tags: vhdl-2019, ieee, verification, vhdlwhiz
First VHDL-2019 examples on EDA playground @tmeissner
#8 3 0 · 2020/08/22 · tags: vhdl-2019, verification, eda-playground, riviera
Create your own VVC for UVVM @Ahmad-Zaklouta
#7 1 6 · 2020/08/19 · tags: verification, simulation, uvvm
What Can GitHub Tell Us About the HDL Industry? (Part 2) @eine
#6 1 0 · 2020/08/19 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) @tmeissner
#5 3 0 · 2020/08/18 tmeissner/psl_with_ghdl · tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage
Addressing VHDL Verification Challenges with OSVVM @tmeissner
#4 4 0 · 2020/08/18 · tags: verification, simulation, osvvm, mentor
What Can GitHub Tell Us About the HDL Industry? (Part 1) @eine
#3 3 0 · 2020/08/18 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit
What Can GitHub Tell Us About the HDL Industry? @eine
#2 3 0 · 2020/08/18 LarsAsplund/github-facts · tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit