VHDL Language Model

Design Goal

• Clearly named classes that model the semantics of VHDL.

• All language constructs (statements, declarations, specifications, …) have their own classes.
  These classes are arranged in a logical hierarchy, with a single common base-class.

• Child objects shall have a reference to their parent.

• Comments will be associated with a particular code object.

• Easy modifications of the object tree.

Elements of the Language Model

• Concepts not defined by VHDL
• Enumerations
• Design Units
• Interface Items
• Subprogram Declarations
• Type Declarations
• Subtype Declarations
• Object Declarations
• Concurrent Statements
• Sequential Statements
• Literals and Expressions