Unittest Summary Report
| Testsuite / Testcase | Testcases | Skipped | Errored | Failed | Passed | Runtime (HH:MM:SS.sss) |
|---|---|---|---|---|---|---|
| ✅TestsuiteSummary | 465 | 0 | 0 | 0 | 465 | 00:00:04.638 |
| ✅unit | 465 | 0 | 0 | 0 | 465 | 00:00:04.638 |
| ✅Analyze | 16 | 0 | 0 | 0 | 16 | 00:00:00.958 |
| ✅IndexDeclaredItems | 2 | 0 | 0 | 0 | 2 | 00:00:00.031 |
| ✅TopLevel | 2 | 0 | 0 | 0 | 2 | 00:00:00.021 |
| ✅VHDLLibrary | 12 | 0 | 0 | 0 | 12 | 00:00:00.906 |
| ✅Hierarchy | 7 | 0 | 0 | 0 | 7 | 00:00:00.096 |
| ✅AllowBlackBox | 4 | 0 | 0 | 0 | 4 | 00:00:00.030 |
| ✅GetAncestor | 3 | 0 | 0 | 0 | 3 | 00:00:00.066 |
| ✅Instantiation | 358 | 0 | 0 | 0 | 358 | 00:00:03.067 |
| ✅Assignment | 16 | 0 | 0 | 0 | 16 | 00:00:00.146 |
| ✅ConcurrentAssignments | 2 | 0 | 0 | 0 | 2 | 00:00:00.016 |
| ✅ConditionalAndSelectedBuildingBlocks | 7 | 0 | 0 | 0 | 7 | 00:00:00.060 |
| ✅SequentialAssignments | 7 | 0 | 0 | 0 | 7 | 00:00:00.070 |
| ✅Base | 26 | 0 | 0 | 0 | 26 | 00:00:00.256 |
| ✅BlockStatementMixinHost | 1 | 0 | 0 | 0 | 1 | 00:00:00.009 |
| ✅BranchMixins | 3 | 0 | 0 | 0 | 3 | 00:00:00.031 |
| ✅ChoicesMixinHost | 1 | 0 | 0 | 0 | 1 | 00:00:00.009 |
| ✅DirectionEnum | 2 | 0 | 0 | 0 | 2 | 00:00:00.017 |
| ✅ModeEnum | 1 | 0 | 0 | 0 | 1 | 00:00:00.020 |
| ✅ModelEntities | 4 | 0 | 0 | 0 | 4 | 00:00:00.062 |
| ✅OptionallyNamedEntity | 3 | 0 | 0 | 0 | 3 | 00:00:00.025 |
| ✅Ranges | 3 | 0 | 0 | 0 | 3 | 00:00:00.023 |
| ✅RangesFromName | 3 | 0 | 0 | 0 | 3 | 00:00:00.023 |
| ✅ReportAndAssertStatementMixins | 3 | 0 | 0 | 0 | 3 | 00:00:00.022 |
| ✅WaveformElements | 2 | 0 | 0 | 0 | 2 | 00:00:00.015 |
| ✅Concurrent | 32 | 0 | 0 | 0 | 32 | 00:00:00.264 |
| ✅CaseGenerateStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.016 |
| ✅ConcurrentAssertStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅ConcurrentBlockStatements | 5 | 0 | 0 | 0 | 5 | 00:00:00.037 |
| ✅ConcurrentProcedureCalls | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅ConcurrentSimpleSignalAssignments | 1 | 0 | 0 | 0 | 1 | 00:00:00.010 |
| ✅ConcurrentStatementsMixinIndexing | 2 | 0 | 0 | 0 | 2 | 00:00:00.017 |
| ✅ForGenerateStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.033 |
| ✅GenerateBranches | 4 | 0 | 0 | 0 | 4 | 00:00:00.026 |
| ✅GenerateCases | 2 | 0 | 0 | 0 | 2 | 00:00:00.016 |
| ✅GenerateChoices | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅GenerateStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅IfGenerateStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.022 |
| ✅Instantiations | 4 | 0 | 0 | 0 | 4 | 00:00:00.030 |
| ✅ProcessStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅Configuration | 13 | 0 | 0 | 0 | 13 | 00:00:00.103 |
| ✅BindingIndications | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅BlockConfigurations | 3 | 0 | 0 | 0 | 3 | 00:00:00.022 |
| ✅ComponentConfigurations | 4 | 0 | 0 | 0 | 4 | 00:00:00.025 |
| ✅EntityAspects | 4 | 0 | 0 | 0 | 4 | 00:00:00.042 |
| ✅Declaration | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅Aliases | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅DesignUnit | 28 | 0 | 0 | 0 | 28 | 00:00:00.208 |
| ✅Architectures | 6 | 0 | 0 | 0 | 6 | 00:00:00.045 |
| ✅Components | 3 | 0 | 0 | 0 | 3 | 00:00:00.021 |
| ✅Configurations | 1 | 0 | 0 | 0 | 1 | 00:00:00.007 |
| ✅Contexts | 3 | 0 | 0 | 0 | 3 | 00:00:00.022 |
| ✅DesignUnits | 4 | 0 | 0 | 0 | 4 | 00:00:00.034 |
| ✅Entities | 1 | 0 | 0 | 0 | 1 | 00:00:00.009 |
| ✅MarkerSubclasses | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅PackageBodies | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅Packages | 3 | 0 | 0 | 0 | 3 | 00:00:00.023 |
| ✅References | 3 | 0 | 0 | 0 | 3 | 00:00:00.019 |
| ✅Expression | 37 | 0 | 0 | 0 | 37 | 00:00:00.381 |
| ✅AggregateElements | 5 | 0 | 0 | 0 | 5 | 00:00:00.033 |
| ✅Aggregates | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅BinaryExpressionFormats | 1 | 0 | 0 | 0 | 1 | 00:00:00.072 |
| ✅BinaryExpressions | 1 | 0 | 0 | 0 | 1 | 00:00:00.010 |
| ✅BitStringLiterals | 7 | 0 | 0 | 0 | 7 | 00:00:00.043 |
| ✅ClassVariables | 3 | 0 | 0 | 0 | 3 | 00:00:00.063 |
| ✅FunctionCallAndAllocation | 3 | 0 | 0 | 0 | 3 | 00:00:00.018 |
| ✅Literals | 6 | 0 | 0 | 0 | 6 | 00:00:00.039 |
| ✅PhysicalLiterals | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅QualifiedExpressions | 1 | 0 | 0 | 0 | 1 | 00:00:00.009 |
| ✅RangeExpressions | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅TernaryExpressions | 1 | 0 | 0 | 0 | 1 | 00:00:00.011 |
| ✅TypeConversions | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅UnaryExpressionFormats | 2 | 0 | 0 | 0 | 2 | 00:00:00.034 |
| ✅UnaryExpressions | 1 | 0 | 0 | 0 | 1 | 00:00:00.007 |
| ✅GenericInstantiation | 7 | 0 | 0 | 0 | 7 | 00:00:00.049 |
| ✅FunctionInstantiations | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅PackageInstantiations | 3 | 0 | 0 | 0 | 3 | 00:00:00.023 |
| ✅ProcedureInstantiations | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅Interface | 39 | 0 | 0 | 0 | 39 | 00:00:00.384 |
| ✅GenericInterfaceItems | 6 | 0 | 0 | 0 | 6 | 00:00:00.051 |
| ✅Groups | 8 | 0 | 0 | 0 | 8 | 00:00:00.048 |
| ✅InterfaceItemRendering | 6 | 0 | 0 | 0 | 6 | 00:00:00.157 |
| ✅ModeViewDeclarations | 6 | 0 | 0 | 0 | 6 | 00:00:00.039 |
| ✅ModeViewSymbols | 2 | 0 | 0 | 0 | 2 | 00:00:00.014 |
| ✅ParameterInterfaceItems | 4 | 0 | 0 | 0 | 4 | 00:00:00.026 |
| ✅ParameterSignalInterfaceItems | 2 | 0 | 0 | 0 | 2 | 00:00:00.015 |
| ✅PortSignalInterfaceItems | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅WithGenericsPortsParametersMixins | 3 | 0 | 0 | 0 | 3 | 00:00:00.021 |
| ✅Model | 59 | 0 | 0 | 0 | 59 | 00:00:00.552 |
| ✅Names | 5 | 0 | 0 | 0 | 5 | 00:00:00.034 |
| ✅PSLEntities | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅SimpleInstance | 18 | 0 | 0 | 0 | 18 | 00:00:00.102 |
| ✅Symbols | 13 | 0 | 0 | 0 | 13 | 00:00:00.077 |
| ✅VHDLDocument | 8 | 0 | 0 | 0 | 8 | 00:00:00.051 |
| ✅VHDLLibrary | 13 | 0 | 0 | 0 | 13 | 00:00:00.277 |
| ✅Name | 14 | 0 | 0 | 0 | 14 | 00:00:00.118 |
| ✅AllNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.009 |
| ✅AttributeNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅IndexedNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅Names | 5 | 0 | 0 | 0 | 5 | 00:00:00.060 |
| ✅OpenNames | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅ParenthesisNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅SelectedNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅SimpleNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅SlicedNames | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅Object | 16 | 0 | 0 | 0 | 16 | 00:00:00.099 |
| ✅Constants | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅DeferredConstants | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅Files | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅ObjBaseBehaviour | 5 | 0 | 0 | 0 | 5 | 00:00:00.034 |
| ✅SharedVariables | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅Signals | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅Variables | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅WithDefaultExpression | 2 | 0 | 0 | 0 | 2 | 00:00:00.012 |
| ✅Sequential | 22 | 0 | 0 | 0 | 22 | 00:00:00.180 |
| ✅CaseStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.007 |
| ✅Cases | 3 | 0 | 0 | 0 | 3 | 00:00:00.016 |
| ✅Choices | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅IfStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.012 |
| ✅LoopControlStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅LoopStatements | 3 | 0 | 0 | 0 | 3 | 00:00:00.053 |
| ✅NullStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅ReturnStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.010 |
| ✅SequentialProcedureCalls | 2 | 0 | 0 | 0 | 2 | 00:00:00.030 |
| ✅SequentialSignalAssignments | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅SequentialSimpleSignalAssignments | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅WaitStatements | 2 | 0 | 0 | 0 | 2 | 00:00:00.012 |
| ✅Subprogram | 9 | 0 | 0 | 0 | 9 | 00:00:00.054 |
| ✅Functions | 2 | 0 | 0 | 0 | 2 | 00:00:00.015 |
| ✅MethodMixinHosts | 4 | 0 | 0 | 0 | 4 | 00:00:00.022 |
| ✅Procedures | 3 | 0 | 0 | 0 | 3 | 00:00:00.017 |
| ✅Symbol | 14 | 0 | 0 | 0 | 14 | 00:00:00.103 |
| ✅ConstrainedSubtypeSymbols | 5 | 0 | 0 | 0 | 5 | 00:00:00.026 |
| ✅NoPropertyReferenceSymbols | 3 | 0 | 0 | 0 | 3 | 00:00:00.021 |
| ✅SimpleReferenceSymbols | 2 | 0 | 0 | 0 | 2 | 00:00:00.035 |
| ✅SubtypeSymbols | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅SymbolBase | 2 | 0 | 0 | 0 | 2 | 00:00:00.010 |
| ✅Type | 24 | 0 | 0 | 0 | 24 | 00:00:00.156 |
| ✅AccessTypes | 1 | 0 | 0 | 0 | 1 | 00:00:00.008 |
| ✅ArrayTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅EnumeratedTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.012 |
| ✅FileTypes | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅IntegerTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.012 |
| ✅ParentAndDocumentationWiringAcrossAllLeafTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.027 |
| ✅PhysicalTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅ProtectedTypeBodies | 3 | 0 | 0 | 0 | 3 | 00:00:00.015 |
| ✅ProtectedTypes | 3 | 0 | 0 | 0 | 3 | 00:00:00.017 |
| ✅RealTypes | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅RecordTypeElements | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅RecordTypes | 2 | 0 | 0 | 0 | 2 | 00:00:00.011 |
| ✅Subtypes | 1 | 0 | 0 | 0 | 1 | 00:00:00.007 |
| ✅Namespace | 84 | 0 | 0 | 0 | 84 | 00:00:00.517 |
| ✅DesignUnits | 1 | 0 | 0 | 0 | 1 | 00:00:00.010 |
| ✅Architectures | 1 | 0 | 0 | 0 | 1 | 00:00:00.010 |
| ✅Duplicates | 11 | 0 | 0 | 0 | 11 | 00:00:00.082 |
| ✅OneDeclarativePart | 4 | 0 | 0 | 0 | 4 | 00:00:00.026 |
| ✅OverloadableDeclarations | 3 | 0 | 0 | 0 | 3 | 00:00:00.020 |
| ✅RegionsSpanningTwoNamespaces | 4 | 0 | 0 | 0 | 4 | 00:00:00.036 |
| ✅Hiding | 13 | 0 | 0 | 0 | 13 | 00:00:00.103 |
| ✅BlocksInsideArchitecture | 3 | 0 | 0 | 0 | 3 | 00:00:00.024 |
| ✅EntityAndArchitecture | 5 | 0 | 0 | 0 | 5 | 00:00:00.041 |
| ✅GeneratesInsideArchitecture | 2 | 0 | 0 | 0 | 2 | 00:00:00.013 |
| ✅NestedBlocks | 3 | 0 | 0 | 0 | 3 | 00:00:00.025 |
| ✅InterfaceItems | 13 | 0 | 0 | 0 | 13 | 00:00:00.071 |
| ✅BlockPorts | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅EntityInterfaceItems | 8 | 0 | 0 | 0 | 8 | 00:00:00.043 |
| ✅PackageGenerics | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅SubprogramInterfaceItems | 3 | 0 | 0 | 0 | 3 | 00:00:00.016 |
| ✅Namespace | 26 | 0 | 0 | 0 | 26 | 00:00:00.139 |
| ✅FindComponent | 6 | 0 | 0 | 0 | 6 | 00:00:00.035 |
| ✅FindObject | 9 | 0 | 0 | 0 | 9 | 00:00:00.044 |
| ✅FindSubtype | 8 | 0 | 0 | 0 | 8 | 00:00:00.047 |
| ✅Namespaces | 3 | 0 | 0 | 0 | 3 | 00:00:00.013 |
| ✅SequentialRegions | 16 | 0 | 0 | 0 | 16 | 00:00:00.087 |
| ✅ProcessNamespaces | 8 | 0 | 0 | 0 | 8 | 00:00:00.042 |
| ✅SubprogramNamespaces | 8 | 0 | 0 | 0 | 8 | 00:00:00.045 |
| ✅Statements | 4 | 0 | 0 | 0 | 4 | 00:00:00.025 |
| ✅BlockStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅CaseGenerateStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅ForGenerateStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.006 |
| ✅IfGenerateStatements | 1 | 0 | 0 | 0 | 1 | 00:00:00.007 |
| ✅ PASSED | 465 | 0 | 0 | 0 | 465 | 00:00:04.638 |
Unittest report generated with pytest and visualized by sphinx-reports.