pyVHDLModel

An abstract VHDL language model.

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.

Copyright Information

copyright:: Copyright 2017-2024 Patrick Lehmann - Bötzingen, Germany
copyright:: Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
license:: Apache License, Version 2.0

Submodules

Classes

VHDLVersion: An enumeration for all possible version numbers for VHDL and VHDL-AMS.
ObjectClass: An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).
DesignUnitKind: A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).
DependencyGraphVertexKind: A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.
DependencyGraphEdgeKind: A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.
ObjectGraphVertexKind: A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.
ObjectGraphEdgeKind: A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.
Design: A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).
Library: A Library represents a VHDL library. It contains all primary and secondary design units.
Document: A Document represents a sourcefile. It contains primary and secondary design units.

Classes

class pyVHDLModel.VHDLVersion(*_)[source]

An enumeration for all possible version numbers for VHDL and VHDL-AMS.

A version can be given as integer or string and is represented as a unified enumeration value.

This enumeration supports compare operators.

Inheritance

Any = -1: Any

VHDL87 = 87: VHDL-1987

VHDL93 = 93: VHDL-1993

AMS93 = 1993: VHDL-AMS-1993

AMS99 = 1999: VHDL-AMS-1999

VHDL2000 = 2000: VHDL-2000

VHDL2002 = 2002: VHDL-2002

VHDL2008 = 2008: VHDL-2008

AMS2017 = 2017: VHDL-AMS-2017

VHDL2019 = 2019: VHDL-2019

Latest = 10000: Latest VHDL (2019)

__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {'00': 2000, '02': 2002, '08': 2008, '17': 2017, '19': 2019, '1987': 87, '1993': 1993, '1999': 1999, '2000': 2000, '2002': 2002, '2008': 2008, '2017': 2017, '2019': 2019, '87': 87, '93': 93, '99': 1999, 'Any': Any, 'Latest': Latest, -1: Any, 0: 2000, 10000: Latest, 17: 2017, 19: 2019, 1987: 87, 1993: 1993, 1999: 1999, 2: 2002, 2000: 2000, 2002: 2002, 2008: 2008, 2017: 2017, 2019: 2019, 8: 2008, 87: 87, 93: 93, 99: 1999}: Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.

__init__(*_)[source]

Patch the embedded MAP dictionary

Return type:: None

classmethod Parse(value)[source]

Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.

Parameters:: value (Union[int, str]) – VHDL/VHDL-AMS year code.
Return type:: VHDLVersion
Returns:: Enumeration value.
Raises:: ValueError – If the year code is not recognized.

__lt__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is less than the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

__le__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is less or equal than the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

__gt__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is greater than the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

__ge__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is greater or equal than the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

__ne__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is unequal to the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

__eq__(other)[source]

Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.

Parameters:: other (-1) – Parameter to compare against.
Return type:: bool
Returns:: True if version is equal to the second operand.
Raises:: TypeError – If parameter other is not of type VHDLVersion.

property IsVHDL: bool

Checks if the version is a VHDL (not VHDL-AMS) version.

Returns:: True if version is a VHDL version.

property IsAMS: bool

Checks if the version is a VHDL-AMS (not VHDL) version.

Returns:: True if version is a VHDL-AMS version.

__str__()[source]

Formats the VHDL version to pattern VHDL'xx or in case of VHDL-AMS to VHDL-AMS'xx.

Return type:: str
Returns:: Formatted VHDL/VHDL-AMS version.

__repr__()[source]

Formats the VHDL/VHDL-AMS version to pattern xxxx.

Return type:: str
Returns:: Formatted VHDL/VHDL-AMS version.

class pyVHDLModel.ObjectClass(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).

In case no object class is defined, Default is used, so the object class is inferred from context.

Inheritance

Default = 0: Object class not defined, thus it’s context dependent.

Constant = 1: Constant

Variable = 2: Variable

Signal = 3: Signal

File = 4: File

Type = 5: Type

Procedure = 6: Procedure

Function = 7: Function

__str__()[source]

Formats the object class.

Return type:: str
Returns:: Formatted object class.

class pyVHDLModel.DesignUnitKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).

Inheritance

Context = 1: Context

Package = 2: Package

PackageBody = 4: Package Body

Entity = 8: Entity

Architecture = 16: Architecture

Configuration = 32: Configuration

Primary = 43: List of primary design units.

Secondary = 20: List of secondary design units.

WithContext = 62: List of design units with a context.

WithDeclaredItems = 30: List of design units having a declaration region.

All = 63: List of all design units.

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_()

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value): Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other): Returns True if self has at least the same flags set as other.

__iter__(): Returns flags in definition order.

__len__(): Return the number of members (no aliases)

__repr__(): Return repr(self).

__str__(): Return str(self).

__bool__(): classes/types should always be True.

__or__(other): Return self|value.

__ror__(other): Return value|self.

__new__(value)

class pyVHDLModel.DependencyGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.

Inheritance

Document = 1: A document (VHDL source file).

Library = 2: A VHDL library.

Context = 4: A context design unit.

Package = 8: A package design unit.

PackageBody = 16: A package body design unit.

Entity = 32: A entity design unit.

Architecture = 64: A architecture design unit.

Component = 128: A VHDL component.

Configuration = 256: A configuration design unit.

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_()

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value): Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other): Returns True if self has at least the same flags set as other.

__iter__(): Returns flags in definition order.

__len__(): Return the number of members (no aliases)

__repr__(): Return repr(self).

__str__(): Return str(self).

__bool__(): classes/types should always be True.

__or__(other): Return self|value.

__ror__(other): Return value|self.

__new__(value)

class pyVHDLModel.DependencyGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.

Inheritance

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_()

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value): Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other): Returns True if self has at least the same flags set as other.

__iter__(): Returns flags in definition order.

__len__(): Return the number of members (no aliases)

__repr__(): Return repr(self).

__str__(): Return str(self).

__bool__(): classes/types should always be True.

__or__(other): Return self|value.

__ror__(other): Return value|self.

__new__(value)

class pyVHDLModel.ObjectGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.

Inheritance

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_()

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value): Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other): Returns True if self has at least the same flags set as other.

__iter__(): Returns flags in definition order.

__len__(): Return the number of members (no aliases)

__repr__(): Return repr(self).

__str__(): Return str(self).

__bool__(): classes/types should always be True.

__or__(other): Return self|value.

__ror__(other): Return value|self.

__new__(value)

class pyVHDLModel.ObjectGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.

Inheritance

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_()

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value): Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value): Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other): Returns True if self has at least the same flags set as other.

__iter__(): Returns flags in definition order.

__len__(): Return the number of members (no aliases)

__repr__(): Return repr(self).

__str__(): Return str(self).

__bool__(): classes/types should always be True.

__or__(other): Return self|value.

__ror__(other): Return value|self.

__new__(value)

class pyVHDLModel.Design(name=None)[source]

A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

It’s the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see Library). When the design is analysed (see Analyze()), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design’s compile order and hierarchy can be iterated. As a second result, the design’s top-level is identified and referenced from the design (see TopLevel).

The design contains references to the following graphs:

DependencyGraph
CompileOrderGraph
HierarchyGraph
ObjectGraph

Inheritance

Parameters:: name (str | None)

__init__(name=None)[source]

Initializes a VHDL design.

Parameters:: name (Optional[str]) – Name of the design.
Return type:: None

_name: Optional[str]: Name of the design

_libraries: Dict[str, Library]: List of all libraries defined for a design.

_documents: List[Document]: List of all documents loaded for a design.

_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: A graph derived from dependency graph containing the order of documents for compilation.

_dependencyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]: The graph of all dependencies in the designs.

_hierarchyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]: A graph derived from dependency graph containing the design hierarchy.

_objectGraph: Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]: The graph of all types and objects in the design.

_toplevel: Union[Entity, Configuration]: When computed, the toplevel design unit is cached in this field.

property Libraries: Dict[str, Library]

Read-only property to access the dictionary of library names and VHDL libraries (_libraries).

Returns:: A dictionary of library names and VHDL libraries.

property Documents: List[Document]

Read-only property to access the list of all documents (VHDL source files) loaded for this design (_documents).

Returns:: A list of all documents.

property CompileOrderGraph: Graph

Read-only property to access the compile-order graph (_compileOrderGraph).

Returns:: Reference to the compile-order graph.

property DependencyGraph: Graph

Read-only property to access the dependency graph (_dependencyGraph).

Returns:: Reference to the dependency graph.

property HierarchyGraph: Graph

Read-only property to access the hierarchy graph (_hierarchyGraph).

Returns:: Reference to the hierarchy graph.

property ObjectGraph: Graph

Read-only property to access the object graph (_objectGraph).

Returns:: Reference to the object graph.

property TopLevel: Entity | Configuration

Read-only property to access the design’s top-level (_toplevel).

When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field toplevel is added to _hierarchyGraph referencing that single element. In addition, the result is cached in _toplevel.

Returns:

Reference to the design’s top-level.

Raises:

VHDLModelException – If the hierarchy graph is not yet computed from dependency graph.
VHDLModelException – If there is more than one top-level.

LoadStdLibrary()[source]

Load the predefined VHDL library std into the design.

This will create a virtual source code file std.vhdl and register VHDL design units of library std to that file.

Return type:: Library
Returns:: The library object of library std.

LoadIEEELibrary()[source]

Load the predefined VHDL library ieee into the design.

This will create a virtual source code file ieee.vhdl and register VHDL design units of library ieee to that file.

Return type:: Library
Returns:: The library object of library ieee.

AddLibrary(library)[source]

Add a VHDL library to the design.

Ensure the libraries name doesn’t collide with existing libraries in the design.
If ok, set the libraries parent reference to the design.

Parameters:

library (Library) – Library object to loaded.

Raises:

LibraryExistsInDesignError – If the library already exists in the design.
LibraryRegisteredToForeignDesignError – If library is already used by a different design.

Return type:

None

GetLibrary(libraryName)[source]

Return an (existing) VHDL library object of name libraryName.

If the requested VHDL library doesn’t exist, a new VHDL library with that name will be created.

Parameters:: libraryName (str) – Name of the requested VHDL library.
Return type:: Library
Returns:: The VHDL library object.

AddDocument(document, library)[source]

Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.

Algorithm

Iterate all entities in the document
1. Check if entity name might exist in target library.
2. Add entity to library and update library membership.
Iterate all architectures in the document
1. Check if architecture name might exist in target library.
2. Add architecture to library and update library membership.
Iterate all packages in the document
1. Check if package name might exist in target library.
2. Add package to library and update library membership.
Iterate all package bodies in the document
1. Check if package body name might exist in target library.
2. Add package body to library and update library membership.
Iterate all configurations in the document
1. Check if configuration name might exist in target library.
2. Add configuration to library and update library membership.
Iterate all contexts in the document
1. Check if context name might exist in target library.
2. Add context to library and update library membership.

Parameters:

document (Document) – The VHDL source code file.
library (Library) – The VHDL library used to register the embedded design units to.

Raises:

LibraryNotRegisteredError – If the given VHDL library is not a library in the design.
EntityExistsInLibraryError – If the processed entity’s name is already existing in the VHDL library.
ArchitectureExistsInLibraryError – If the processed architecture’s name is already existing in the VHDL library.
PackageExistsInLibraryError – If the processed package’s name is already existing in the VHDL library.
PackageBodyExistsError – If the processed package body’s name is already existing in the VHDL library.
ConfigurationExistsInLibraryError – If the processed configuration’s name is already existing in the VHDL library.
ContextExistsInLibraryError – If the processed context’s name is already existing in the VHDL library.

Return type:

None

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the design.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

Iterate all VHDL libraries.
1. Iterate all contexts in that library.
2. Iterate all packages in that library.
3. Iterate all package bodies in that library.
4. Iterate all entites in that library.
5. Iterate all architectures in that library.
6. Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the design.

See also

pyVHDLModel.Library.IterateDesignUnits(): Iterate all design units in the library.
pyVHDLModel.Document.IterateDesignUnits(): Iterate all design units in the document.

Analyze()[source]

Analyze the whole design.

Return type:: None

Algorithm

Analyze dependencies of design units.
This will also yield the design hierarchy and the compiler order.
Analyze dependencies of types and objects.

See also

AnalyzeDependencies(): Analyze the dependencies of design units.
AnalyzeObjects(): Analyze the dependencies of types and objects.

AnalyzeDependencies()[source]

Analyze the dependencies of design units.

Return type:: None

Algorithm

Create all vertices of the dependency graph by iterating all design units in all libraries.
→ CreateDependencyGraph()
Create the compile order graph.
→ CreateCompileOrderGraph()
Index all packages.
→ IndexPackages()
Index all architectures.
→ IndexArchitectures()
Link all contexts
→ LinkContexts()
Link all architectures.
→ LinkArchitectures()
Link all package bodies.
→ LinkPackageBodies()
Link all library references.
→ LinkLibraryReferences()
Link all package references.
→ LinkPackageReferences()
Link all context references.
→ LinkContextReferences()
Link all components.
→ LinkComponents()
Link all instantiations.
→ LinkInstantiations()
Create the hierarchy graph.
→ CreateHierarchyGraph()
Compute the compile order.
→ ComputeCompileOrder()

AnalyzeObjects()[source]

Analyze the dependencies of types and objects.

Return type:: None

Algorithm

Index all entities.
→ IndexEntities()
Index all package bodies.
→ IndexPackageBodies()
Import objects.
→ ImportObjects()
Create the type and object graph.
→ CreateTypeAndObjectGraph()

CreateDependencyGraph()[source]

Create all vertices of the dependency graph by iterating all design units in all libraries.

This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods.
See AnalyzeDependencies() for these methods and their algorithmic order.

Each vertex has the following properties: :rtype: None

The vertex’ ID is the design unit’s identifier.
The vertex’ value references the design unit.
A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.
A key-value-pair called predefined denotes if the referenced design unit is a predefined language entity.

Algorithm

Iterate all libraries in the design.
- Create a vertex for that library and reference the library by the vertex’ value field.
  In return, set the library’s _dependencyVertex field to reference the created vertex.
1. Iterate all contexts in that library.
  - Create a vertex for that context and reference the context by the vertex’ value field.
    In return, set the context’s _dependencyVertex field to reference the created vertex.
2. Iterate all packages in that library.
  - Create a vertex for that package and reference the package by the vertex’ value field.
    In return, set the package’s _dependencyVertex field to reference the created vertex.
3. Iterate all package bodies in that library.
  - Create a vertex for that package body and reference the package body by the vertex’ value field.
    In return, set the package body’s _dependencyVertex field to reference the created vertex.
4. Iterate all entities in that library.
  - Create a vertex for that entity and reference the entity by the vertex’ value field.
    In return, set the entity’s _dependencyVertex field to reference the created vertex.
5. Iterate all architectures in that library.
  - Create a vertex for that architecture and reference the architecture by the vertex’ value field.
    In return, set the architecture’s _dependencyVertex field to reference the created vertex.
6. Iterate all configurations in that library.
  - Create a vertex for that configuration and reference the configuration by the vertex’ value field.
    In return, set the configuration’s _dependencyVertex field to reference the created vertex.

Return type:: None

CreateCompileOrderGraph()[source]

Create a compile-order graph with bidirectional references to the dependency graph.

Add vertices representing a document (VHDL source file) to the dependency graph. Each “document” vertex in dependency graph is copied into the compile-order graph and bidirectionally referenced.

In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in document relationship.

Each added vertex has the following properties: :rtype: None

The vertex’ ID is the document’s filename.
The vertex’ value references the document.
A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.
A key-value-pair called predefined does not exist.

Algorithm

Iterate all documents in the design.
- Create a vertex for that document and reference the document by the vertex’ value field.
  In return, set the documents’s _dependencyVertex field to reference the created vertex.
- Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally.
  In addition, set the documents’s _dependencyVertex field to reference the copied vertex.
  - Add a key-value-pair called compileOrderVertex to the dependency graph’s vertex.
  - Add a key-value-pair called dependencyVertex to the compiler-order graph’s vertex.
1. Iterate the documents design units and create an edge from the design unit’s corresponding dependency vertex to the documents corresponding dependency vertex. This expresses a “design unit is located in document” relation.
  - Add a key-value-pair called kind` denoting the edge’s kind as an enumeration value of type DependencyGraphEdgeKind.

Return type:: None

LinkContexts()[source]

Resolves and links all items (library clauses, use clauses and nested context references) in contexts.

It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By default, the working library is implicitly referenced in _referencedLibraries. In addition, a new empty dictionary is created in _referencedPackages and _referencedContexts for that working library.

At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each referenced library an entry in _referencedLibraries is generated and new empty dictionaries in _referencedPackages and _referencedContexts for that working library. In addition, a vertex in the dependency graph is added for that relationship.

At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each referenced package,

Return type:: None

LinkArchitectures()[source]

Link all architectures to corresponding entities in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all architecture groups (grouped per entity symbol’s name). → pyVHDLModel.Library.LinkArchitectures()
  - Check if entity symbol’s name exists as an entity in this library.
  1. For each architecture in the same architecture group:
    - Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.
    - Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity
    - Set parent namespace of architecture’s namespace to the entitie’s namespace.
    - Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

See also

LinkPackageBodies(): Link all package bodies to corresponding packages in all libraries.

LinkPackageBodies()[source]

Link all package bodies to corresponding packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all package bodies. → pyVHDLModel.Library.LinkPackageBodies()
  - Check if package body symbol’s name exists as a package in this library.
  - Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.
  - Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package
  - Set parent namespace of package body’s namespace to the package’s namespace.
  - Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

See also

LinkArchitectures(): Link all architectures to corresponding entities in all libraries.

IndexPackages()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexPackages()
  - Index all declared items in that package.
    → pyVHDLModel.DesignUnit.Package.IndexDeclaredItems()

See also

IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IndexPackageBodies()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexPackageBodies()
  - Index all declared items in that package body.
    → pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IndexEntities()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexEntities()
  - Index all declared items in that entity.
    → pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexArchitectures(): Index all declared items in all architectures in all libraries.

IndexArchitectures()[source]

Index all declared items in all packages in all libraries.

Return type:: None

Algorithm

Iterate all libraries:
1. Iterate all packages
  → pyVHDLModel.Library.IndexArchitectures()
  - Index all declared items in that architecture.
    → pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in all packages in all libraries.
IndexPackageBodies(): Index all declared items in all package bodies in all libraries.
IndexEntities(): Index all declared items in all entities in all libraries.

CreateHierarchyGraph()[source]

Create the hierarchy graph from dependency graph.

Return type:: None

Algorithm

Iterate all vertices corresponding to entities and architectures in the dependency graph:
- Copy these vertices to the hierarchy graph and create a bidirectional linking.
  In addition, set the referenced design unit’s _hierarchyVertex field to reference the copied vertex.
  - Add a key-value-pair called hierarchyVertex to the dependency graph’s vertex.
  - Add a key-value-pair called dependencyVertex to the hierarchy graph’s vertex.
Iterate all architectures …

Todo

Design::CreateHierarchyGraph describe algorithm
1. Iterate all outbound edges
  
  Todo
  
  Design::CreateHierarchyGraph describe algorithm

IterateDocumentsInCompileOrder()[source]

Iterate all document in compile-order.

Algorithm

Check if compile-order graph was populated with vertices and its vertices are linked by edges.

Iterate compile-order graph in topological order.
pyTooling.Graph.Graph.IterateTopologically()
- yield the compiler-order vertex’ referenced document.

Return type:: Generator[Document, None, None]
Returns:: A generator to iterate all documents in compile-order in the design.
Raises:: VHDLModelException – If compile-order was not computed.

See also

Todo

missing text

pyVHDLModel.Design.ComputeCompileOrder()

__repr__()[source]

Formats a representation of the design.

Format: Document: 'my_design'

Return type:: str
Returns:: String representation of the design.

__str__()

Formats a representation of the design.

Format: Document: 'my_design'

Return type:: str
Returns:: String representation of the design.

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Library(identifier, parent=None)[source]

A Library represents a VHDL library. It contains all primary and secondary design units.

Inheritance

Parameters:

identifier (str)
parent (ModelEntity)

__init__(identifier, parent=None)[source]

Initializes a VHDL model entity.

Parameters:

parent (ModelEntity) – The parent model entity of this entity.
identifier (str)

Return type:

None

_contexts: Dict[str, Context]: Dictionary of all contexts defined in a library.

_configurations: Dict[str, Configuration]: Dictionary of all configurations defined in a library.

_entities: Dict[str, Entity]: Dictionary of all entities defined in a library.

_architectures: Dict[str, Dict[str, Architecture]]: Dictionary of all architectures defined in a library.

_packages: Dict[str, Package]: Dictionary of all packages defined in a library.

_packageBodies: Dict[str, PackageBody]: Dictionary of all package bodies defined in a library.

_dependencyVertex: Vertex[None, None, str, Union[Library, DesignUnit], None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

property Contexts: Dict[str, Context]: Returns a list of all context declarations declared in this library.

property Configurations: Dict[str, Configuration]: Returns a list of all configuration declarations declared in this library.

property Entities: Dict[str, Entity]: Returns a list of all entity declarations declared in this library.

property Architectures: Dict[str, Dict[str, Architecture]]: Returns a list of all architectures declarations declared in this library.

property Packages: Dict[str, Package]: Returns a list of all package declarations declared in this library.

property PackageBodies: Dict[str, PackageBody]: Returns a list of all package body declarations declared in this library.

property DependencyVertex: Vertex

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

The dependency vertex references this library by its value field.

Returns:: The corresponding dependency vertex.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the library.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

Iterate all contexts in that library.
Iterate all packages in that library.
Iterate all package bodies in that library.
Iterate all entites in that library.
Iterate all architectures in that library.
Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the library.

See also

pyVHDLModel.Design.IterateDesignUnits(): Iterate all design units in the design.
pyVHDLModel.Document.IterateDesignUnits(): Iterate all design units in the document.

LinkArchitectures()[source]

Link all architectures to corresponding entities.

Return type:: None

Algorithm

Iterate all architecture groups (grouped per entity symbol’s name).
- Check if entity symbol’s name exists as an entity in this library.
1. For each architecture in the same architecture group:
  - Add architecture to entities architecture dictionary pyVHDLModel.DesignUnit.Entity._architectures.
  - Assign found entity to architecture’s entity symbol pyVHDLModel.DesignUnit.Architecture._entity
  - Set parent namespace of architecture’s namespace to the entitie’s namespace.
  - Add an edge in the dependency graph from the architecture’s corresponding dependency vertex to the entity’s corresponding dependency vertex.

Raises:

VHDLModelException – If entity name doesn’t exist.
VHDLModelException – If architecture name already exists for entity.

Return type:

None

See also

LinkPackageBodies(): Link all package bodies to corresponding packages.

LinkPackageBodies()[source]

Link all package bodies to corresponding packages.

Return type:: None

Algorithm

Iterate all package bodies.
- Check if package body symbol’s name exists as a package in this library.
- Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.
- Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package
- Set parent namespace of package body’s namespace to the package’s namespace.
- Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

Raises:: VHDLModelException – If package name doesn’t exist.
Return type:: None

See also

LinkArchitectures(): Link all architectures to corresponding entities.

IndexPackages()[source]

Index declared items in all packages.

Return type:: None

Algorithm

Iterate all packages:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Package.IndexDeclaredItems()

See also

IndexPackageBodies(): Index all declared items in a package body.
IndexEntities(): Index all declared items in an entity.
IndexArchitectures(): Index all declared items in an architecture.

IndexPackageBodies()[source]

Index declared items in all package bodies.

Return type:: None

Algorithm

Iterate all package bodies:
- Index all declared items.
  → pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexEntities(): Index all declared items in an entity.
IndexArchitectures(): Index all declared items in an architecture.

IndexEntities()[source]

Index declared items in all entities.

Return type:: None

Algorithm

Iterate all entities:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexPackageBodies(): Index all declared items in a package body.
IndexArchitectures(): Index all declared items in an architecture.

IndexArchitectures()[source]

Index declared items in all architectures.

Return type:: None

Algorithm

Iterate all architectures:
- Index all declared items.
  → pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems()

See also

IndexPackages(): Index all declared items in a package.
IndexPackageBodies(): Index all declared items in a package body.
IndexEntities(): Index all declared items in an entity.

__repr__()[source]

Formats a representation of the library.

Format: Library: 'my_library'

Return type:: str
Returns:: String representation of the library.

__str__()

Formats a representation of the library.

Format: Library: 'my_library'

Return type:: str
Returns:: String representation of the library.

_identifier: str: The identifier of a model entity.

_normalizedIdentifier: str: The normalized (lower case) identifier of a model entity.

property Identifier: str

Returns a model entity’s identifier (name).

Returns:: Name of a model entity.

property NormalizedIdentifier: str

Returns a model entity’s normalized identifier (lower case name).

Returns:: Normalized name of a model entity.

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Document(path, documentation=None, parent=None)[source]

A Document represents a sourcefile. It contains primary and secondary design units.

Inheritance

Parameters:

path (Path)
documentation (str | None)
parent (ModelEntity)

__init__(path, documentation=None, parent=None)[source]

Initializes a VHDL model entity.

Parameters:

parent (ModelEntity) – The parent model entity of this entity.
path (Path)
documentation (str | None)

Return type:

None

_path: Path: path to the document. None if virtual document.

_designUnits: List[DesignUnit]: List of all design units defined in a document.

_contexts: Dict[str, Context]: Dictionary of all contexts defined in a document.

_configurations: Dict[str, Configuration]: Dictionary of all configurations defined in a document.

_entities: Dict[str, Entity]: Dictionary of all entities defined in a document.

_architectures: Dict[str, Dict[str, Architecture]]: Dictionary of all architectures defined in a document.

_packages: Dict[str, Package]: Dictionary of all packages defined in a document.

_packageBodies: Dict[str, PackageBody]: Dictionary of all package bodies defined in a document.

_verificationUnits: Dict[str, VerificationUnit]: Dictionary of all PSL verification units defined in a document.

_verificationProperties: Dict[str, VerificationProperty]: Dictionary of all PSL verification properties defined in a document.

_verificationModes: Dict[str, VerificationMode]: Dictionary of all PSL verification modes defined in a document.

_documentation: Optional[str]: The associated documentation of a model entity.

property Documentation: str | None

Returns a model entity’s associated documentation.

Returns:: Associated documentation of a model entity.

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

_dependencyVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the dependency graph representing the document.
This reference is set by CreateCompileOrderGraph().

_compileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]: Reference to the vertex in the compile-order graph representing the document.
This reference is set by CreateCompileOrderGraph().

_AddEntity(item)[source]

Add an entity to the document’s lists of design units.

Parameters:

item (Entity) – Entity object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Entity.
VHDLModelException – If entity name already exists in document.

Return type:

None

_AddArchitecture(item)[source]

Add an architecture to the document’s lists of design units.

Parameters:

item (Architecture) – Architecture object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Architecture.
VHDLModelException – If architecture name already exists for the referenced entity name in document.

Return type:

None

_AddPackage(item)[source]

Add a package to the document’s lists of design units.

Parameters:

item (Package) – Package object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Package.
VHDLModelException – If package name already exists in document.

Return type:

None

_AddPackageBody(item)[source]

Add a package body to the document’s lists of design units.

Parameters:

item (PackageBody) – Package body object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type PackageBody.
VHDLModelException – If package body name already exists in document.

Return type:

None

_AddContext(item)[source]

Add a context to the document’s lists of design units.

Parameters:

item (Context) – Context object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Context.
VHDLModelException – If context name already exists in document.

Return type:

None

_AddConfiguration(item)[source]

Add a configuration to the document’s lists of design units.

Parameters:

item (Configuration) – Configuration object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type Configuration.
VHDLModelException – If configuration name already exists in document.

Return type:

None

_AddDesignUnit(item)[source]

Add a design unit to the document’s lists of design units.

Parameters:

item (DesignUnit) – Configuration object to be added to the document.

Raises:

TypeError – If parameter ‘item’ is not of type DesignUnit.
ValueError – If parameter ‘item’ is an unknown DesignUnit.
VHDLModelException – If configuration name already exists in document.

Return type:

None

property Path: Path

Read-only property to access the document’s path (_path).

Returns:: The path of this document.

property DesignUnits: List[DesignUnit]

Read-only property to access a list of all design units declarations found in this document (_designUnits).

Returns:: List of all design units.

property Contexts: Dict[str, Context]

Read-only property to access a list of all context declarations found in this document (_contexts).

Returns:: List of all contexts.

property Configurations: Dict[str, Configuration]

Read-only property to access a list of all configuration declarations found in this document (_configurations).

Returns:: List of all configurations.

property Entities: Dict[str, Entity]

Read-only property to access a list of all entity declarations found in this document (_entities).

Returns:: List of all entities.

property Architectures: Dict[str, Dict[str, Architecture]]

Read-only property to access a list of all architecture declarations found in this document (_architectures).

Returns:: List of all architectures.

property Packages: Dict[str, Package]

Read-only property to access a list of all package declarations found in this document (_packages).

Returns:: List of all packages.

property PackageBodies: Dict[str, PackageBody]

Read-only property to access a list of all package body declarations found in this document (_packageBodies).

Returns:: List of all package bodies.

property VerificationUnits: Dict[str, VerificationUnit]

Read-only property to access a list of all verification unit declarations found in this document (_verificationUnits).

Returns:: List of all verification units.

property VerificationProperties: Dict[str, VerificationProperty]

Read-only property to access a list of all verification properties declarations found in this document (_verificationProperties).

Returns:: List of all verification properties.

property VerificationModes: Dict[str, VerificationMode]

Read-only property to access a list of all verification modes declarations found in this document (_verificationModes).

Returns:: List of all verification modes.

property CompileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

Read-only property to access the corresponding compile-order vertex (_compileOrderVertex).

The compile-order vertex references this document by its value field.

Returns:: The corresponding compile-order vertex.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the document.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

If contexts are selected in the filter:
1. Iterate all contexts in that library.
If packages are selected in the filter:
1. Iterate all packages in that library.
If package bodies are selected in the filter:
1. Iterate all package bodies in that library.
If entites are selected in the filter:
1. Iterate all entites in that library.
If architectures are selected in the filter:
1. Iterate all architectures in that library.
If configurations are selected in the filter:
1. Iterate all configurations in that library.

Parameters:: filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.
Return type:: Generator[DesignUnit, None, None]
Returns:: A generator to iterate all matched design units in the document.

See also

pyVHDLModel.Design.IterateDesignUnits(): Iterate all design units in the design.
pyVHDLModel.Library.IterateDesignUnits(): Iterate all design units in the library.

__repr__()[source]

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:: str
Returns:: String representation of the document.

__str__()

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:: str
Returns:: String representation of the document.