pyVHDLModel
An abstract VHDL language model.
This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
Copyright Information
- copyright:
Copyright 2017-2023 Patrick Lehmann - Bötzingen, Germany
- copyright:
Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
- license:
Apache License, Version 2.0
Submodules
- pyVHDLModel.Association
- pyVHDLModel.Base
- pyVHDLModel.Common
- pyVHDLModel.Concurrent
- pyVHDLModel.Declaration
- pyVHDLModel.DesignUnit
- pyVHDLModel.Exception
- pyVHDLModel.Expression
- pyVHDLModel.IEEE
- pyVHDLModel.Instantiation
- pyVHDLModel.Interface
- pyVHDLModel.Name
- pyVHDLModel.Namespace
- pyVHDLModel.Object
- pyVHDLModel.PSLModel
- pyVHDLModel.Predefined
- pyVHDLModel.Regions
- pyVHDLModel.STD
- pyVHDLModel.Sequential
- pyVHDLModel.Subprogram
- pyVHDLModel.Symbol
- pyVHDLModel.Type
Classes
VHDLVersion
: An enumeration for all possible version numbers for VHDL and VHDL-AMS.ObjectClass
: AnObjectClass
is an enumeration. It represents an object’s class (constant
,signal
, …).DesignUnitKind
: Support for flagsDependencyGraphVertexKind
: Support for flagsDependencyGraphEdgeKind
: Support for flagsObjectGraphVertexKind
: Support for flagsObjectGraphEdgeKind
: Support for flagsDesign
: ADesign
represents all loaded and analysed files (seeDocument
). It’s the root of thisLibrary
: ALibrary
represents a VHDL library. It contains all primary and secondary design units.Document
: ADocument
represents a sourcefile. It contains primary and secondary design units.
Classes
- class pyVHDLModel.VHDLVersion(*_)[source]
An enumeration for all possible version numbers for VHDL and VHDL-AMS.
A version can be given as integer or string and is represented as a unified enumeration value.
This enumeration supports compare operators.
Inheritance
- Any = -1
Any
- VHDL87 = 87
VHDL-1987
- VHDL93 = 93
VHDL-1993
- AMS93 = 1993
VHDL-AMS-1993
- AMS99 = 1999
VHDL-AMS-1999
- VHDL2000 = 2000
VHDL-2000
- VHDL2002 = 2002
VHDL-2002
- VHDL2008 = 2008
VHDL-2008
- AMS2017 = 2017
VHDL-AMS-2017
- VHDL2019 = 2019
VHDL-2019
- Latest = 10000
Latest VHDL (2019)
-
__VERSION_MAPPINGS__:
Dict
[Union
[int
,str
],Enum
] = {'00': 2000, '02': 2002, '08': 2008, '17': 2017, '19': 2019, '1987': 87, '1993': 1993, '1999': 1999, '2000': 2000, '2002': 2002, '2008': 2008, '2017': 2017, '2019': 2019, '87': 87, '93': 93, '99': 1999, 'Any': Any, 'Latest': Latest, -1: Any, 0: 2000, 10000: Latest, 17: 2017, 19: 2019, 1987: 87, 1993: 1993, 1999: 1999, 2: 2002, 2000: 2000, 2002: 2002, 2008: 2008, 2017: 2017, 2019: 2019, 8: 2008, 87: 87, 93: 93, 99: 1999} Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.
- classmethod Parse(value)[source]
Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.
- Parameters:
- Return type:
- Returns:
Enumeration value.
- Raises:
ValueError – If the year code is not recognized.
- __lt__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is less than the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- __le__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is less or equal than the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- __gt__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is greater than the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- __ge__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is greater or equal than the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- __ne__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is unequal to the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- __eq__(other)[source]
Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.
- Parameters:
other (-1) – Parameter to compare against.
- Return type:
- Returns:
True if version is equal to the second operand.
- Raises:
TypeError – If parameter
other
is not of typeVHDLVersion
.
- property IsVHDL: bool
Checks if the version is a VHDL (not VHDL-AMS) version.
- Returns:
True if version is a VHDL version.
- property IsAMS: bool
Checks if the version is a VHDL-AMS (not VHDL) version.
- Returns:
True if version is a VHDL-AMS version.
- __str__()[source]
Formats the VHDL version to pattern
VHDL'xx
or in case of VHDL-AMS toVHDL-AMS'xx
.- Return type:
- Returns:
Formatted VHDL/VHDL-AMS version.
- __repr__()[source]
Formats the VHDL/VHDL-AMS version to pattern
xxxx
.- Return type:
- Returns:
Formatted VHDL/VHDL-AMS version.
- __hash__ = None
- class pyVHDLModel.ObjectClass(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
An
ObjectClass
is an enumeration. It represents an object’s class (constant
,signal
, …).In case no object class is defined,
Default
is used, so the object class is inferred from context.Inheritance
- Default = 0
Object class not defined, thus it’s context dependent.
- Constant = 1
Constant
- Variable = 2
Variable
- Signal = 3
Signal
- File = 4
File
- Type = 5
Type
- Procedure = 6
Procedure
- Function = 7
Function
- class pyVHDLModel.DesignUnitKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
Inheritance
- static _generate_next_value_(name, start, count, last_values)
Generate the next value when not given.
name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None
- _numeric_repr_()
Return the canonical string representation of the object.
For many object types, including most builtins, eval(repr(obj)) == obj.
- classmethod _iter_member_by_value_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_by_def_(value)
Extract all members from the value in definition order.
- classmethod _missing_(value)
Create a composite member containing all canonical members present in value.
If non-member values are present, result depends on _boundary_ setting.
- __contains__(other)
Returns True if self has at least the same flags set as other.
- __iter__()
Returns flags in definition order.
- __len__()
Return the number of members (no aliases)
- __repr__()
Return repr(self).
- __str__()
Return str(self).
- __bool__()
classes/types should always be True.
- __or__(other)
Return self|value.
- __ror__(other)
Return value|self.
- __new__(value)
- class pyVHDLModel.DependencyGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
Inheritance
- static _generate_next_value_(name, start, count, last_values)
Generate the next value when not given.
name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None
- _numeric_repr_()
Return the canonical string representation of the object.
For many object types, including most builtins, eval(repr(obj)) == obj.
- classmethod _iter_member_by_value_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_by_def_(value)
Extract all members from the value in definition order.
- classmethod _missing_(value)
Create a composite member containing all canonical members present in value.
If non-member values are present, result depends on _boundary_ setting.
- __contains__(other)
Returns True if self has at least the same flags set as other.
- __iter__()
Returns flags in definition order.
- __len__()
Return the number of members (no aliases)
- __repr__()
Return repr(self).
- __str__()
Return str(self).
- __bool__()
classes/types should always be True.
- __or__(other)
Return self|value.
- __ror__(other)
Return value|self.
- __new__(value)
- class pyVHDLModel.DependencyGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
Inheritance
- static _generate_next_value_(name, start, count, last_values)
Generate the next value when not given.
name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None
- _numeric_repr_()
Return the canonical string representation of the object.
For many object types, including most builtins, eval(repr(obj)) == obj.
- classmethod _iter_member_by_value_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_by_def_(value)
Extract all members from the value in definition order.
- classmethod _missing_(value)
Create a composite member containing all canonical members present in value.
If non-member values are present, result depends on _boundary_ setting.
- __contains__(other)
Returns True if self has at least the same flags set as other.
- __iter__()
Returns flags in definition order.
- __len__()
Return the number of members (no aliases)
- __repr__()
Return repr(self).
- __str__()
Return str(self).
- __bool__()
classes/types should always be True.
- __or__(other)
Return self|value.
- __ror__(other)
Return value|self.
- __new__(value)
- class pyVHDLModel.ObjectGraphVertexKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
Inheritance
- static _generate_next_value_(name, start, count, last_values)
Generate the next value when not given.
name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None
- _numeric_repr_()
Return the canonical string representation of the object.
For many object types, including most builtins, eval(repr(obj)) == obj.
- classmethod _iter_member_by_value_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_by_def_(value)
Extract all members from the value in definition order.
- classmethod _missing_(value)
Create a composite member containing all canonical members present in value.
If non-member values are present, result depends on _boundary_ setting.
- __contains__(other)
Returns True if self has at least the same flags set as other.
- __iter__()
Returns flags in definition order.
- __len__()
Return the number of members (no aliases)
- __repr__()
Return repr(self).
- __str__()
Return str(self).
- __bool__()
classes/types should always be True.
- __or__(other)
Return self|value.
- __ror__(other)
Return value|self.
- __new__(value)
- class pyVHDLModel.ObjectGraphEdgeKind(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
Inheritance
- static _generate_next_value_(name, start, count, last_values)
Generate the next value when not given.
name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None
- _numeric_repr_()
Return the canonical string representation of the object.
For many object types, including most builtins, eval(repr(obj)) == obj.
- classmethod _iter_member_by_value_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_(value)
Extract all members from the value in definition (i.e. increasing value) order.
- classmethod _iter_member_by_def_(value)
Extract all members from the value in definition order.
- classmethod _missing_(value)
Create a composite member containing all canonical members present in value.
If non-member values are present, result depends on _boundary_ setting.
- __contains__(other)
Returns True if self has at least the same flags set as other.
- __iter__()
Returns flags in definition order.
- __len__()
Return the number of members (no aliases)
- __repr__()
Return repr(self).
- __str__()
Return str(self).
- __bool__()
classes/types should always be True.
- __or__(other)
Return self|value.
- __ror__(other)
Return value|self.
- __new__(value)
- class pyVHDLModel.Design(name=None)[source]
A
Design
represents all loaded and analysed files (seeDocument
). It’s the root of this document-object-model (DOM). It contains at least one VHDL library (seeLibrary
).Inheritance
- Parameters:
name (str)
- __init__(name=None)[source]
Initializes a VHDL design.
- Parameters:
name (
str
) – Name of the design.
-
_compileOrderGraph:
Graph
[None
,None
,None
,None
,None
,None
,None
,None
,None
,Document
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
] A graph derived from dependency graph containing the order of documents for compilation.
-
_dependencyGraph:
Graph
[None
,None
,None
,None
,None
,None
,None
,None
,str
,DesignUnit
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
] The graph of all dependencies in the designs.
-
_hierarchyGraph:
Graph
[None
,None
,None
,None
,None
,None
,None
,None
,str
,DesignUnit
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
] A graph derived from dependency graph containing the design hierarchy.
-
_objectGraph:
Graph
[None
,None
,None
,None
,None
,None
,None
,None
,str
,Obj
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
,None
] The graph of all types and objects in the design.
-
_toplevel:
Union
[Entity
,Configuration
] When computed, the toplevel design unit is cached in this field.
- LinkContexts()[source]
Resolves and links all items (library clauses, use clauses and nested context references) in contexts.
It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By default, the working library is implicitly referenced in
_referencedLibraries
. In addition, a new empty dictionary is created in_referencedPackages
and_referencedContexts
for that working library.At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each referenced library an entry in
_referencedLibraries
is generated and new empty dictionaries in_referencedPackages
and_referencedContexts
for that working library. In addition, a vertex in the dependency graph is added for that relationship.At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each references package,
- Return type:
- class property HasClassAttributes: bool
Check if class has Attributes.
- Returns:
True
, if the class has Attributes.
- class property HasMethodAttributes: bool
Check if class has any method with Attributes.
- Returns:
True
, if the class has any method with Attributes.
- property Parent: ModelEntity
Returns a reference to the parent entity.
- Returns:
Parent entity.
-
_parent:
ModelEntity
Reference to a parent entity in the model.
- class pyVHDLModel.Library(identifier)[source]
A
Library
represents a VHDL library. It contains all primary and secondary design units.Inheritance
- Parameters:
identifier (str)
-
_configurations:
Dict
[str
,Configuration
] Dictionary of all configurations defined in a library.
-
_architectures:
Dict
[str
,Dict
[str
,Architecture
]] Dictionary of all architectures defined in a library.
-
_packageBodies:
Dict
[str
,PackageBody
] Dictionary of all package bodies defined in a library.
- property Contexts: Dict[str, Context]
Returns a list of all context declarations declared in this library.
- property Configurations: Dict[str, Configuration]
Returns a list of all configuration declarations declared in this library.
- property Entities: Dict[str, Entity]
Returns a list of all entity declarations declared in this library.
- property Architectures: Dict[str, Dict[str, Architecture]]
Returns a list of all architectures declarations declared in this library.
- property Packages: Dict[str, Package]
Returns a list of all package declarations declared in this library.
- property PackageBodies: Dict[str, PackageBody]
Returns a list of all package body declarations declared in this library.
- class property HasClassAttributes: bool
Check if class has Attributes.
- Returns:
True
, if the class has Attributes.
- class property HasMethodAttributes: bool
Check if class has any method with Attributes.
- Returns:
True
, if the class has any method with Attributes.
- property Identifier: str
Returns a model entity’s identifier (name).
- Returns:
Name of a model entity.
- property NormalizedIdentifier: str
Returns a model entity’s normalized identifier (lower case name).
- Returns:
Normalized name of a model entity.
- property Parent: ModelEntity
Returns a reference to the parent entity.
- Returns:
Parent entity.
-
_parent:
ModelEntity
Reference to a parent entity in the model.
- class pyVHDLModel.Document(path, documentation=None)[source]
A
Document
represents a sourcefile. It contains primary and secondary design units.Inheritance
-
_designUnits:
List
[DesignUnit
] List of all design units defined in a document.
-
_configurations:
Dict
[str
,Configuration
] Dictionary of all configurations defined in a document.
-
_architectures:
Dict
[str
,Dict
[str
,Architecture
]] Dictionary of all architectures defined in a document.
-
_packageBodies:
Dict
[str
,PackageBody
] Dictionary of all package bodies defined in a document.
-
_verificationUnits:
Dict
[str
,VerificationUnit
] Dictionary of all PSL verification units defined in a document.
-
_verificationProperties:
Dict
[str
,VerificationProperty
] Dictionary of all PSL verification properties defined in a document.
-
_verificationModes:
Dict
[str
,VerificationMode
] Dictionary of all PSL verification modes defined in a document.
- property Documentation: str | None
Returns a model entity’s associated documentation.
- Returns:
Associated documentation of a model entity.
- class property HasClassAttributes: bool
Check if class has Attributes.
- Returns:
True
, if the class has Attributes.
- class property HasMethodAttributes: bool
Check if class has any method with Attributes.
- Returns:
True
, if the class has any method with Attributes.
- property Parent: ModelEntity
Returns a reference to the parent entity.
- Returns:
Parent entity.
-
_parent:
ModelEntity
Reference to a parent entity in the model.
- property DesignUnits: List[DesignUnit]
Returns a list of all design units declarations found in this document.
- property Contexts: Dict[str, Context]
Returns a list of all context declarations found in this document.
- property Configurations: Dict[str, Configuration]
Returns a list of all configuration declarations found in this document.
- property Entities: Dict[str, Entity]
Returns a list of all entity declarations found in this document.
- property Architectures: Dict[str, Dict[str, Architecture]]
Returns a list of all architecture declarations found in this document.
- property Packages: Dict[str, Package]
Returns a list of all package declarations found in this document.
- property PackageBodies: Dict[str, PackageBody]
Returns a list of all package body declarations found in this document.
- property VerificationUnits: Dict[str, VerificationUnit]
Returns a list of all verification unit declarations found in this document.
- property VerificationProperties: Dict[str, VerificationProperty]
Returns a list of all verification property declarations found in this document.
- property VerificationModes: Dict[str, VerificationMode]
Returns a list of all verification mode declarations found in this document.
-
_designUnits: