pyVHDLModel

An abstract VHDL language model.

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.

Copyright Information

copyright:

Copyright 2017-2026 Patrick Lehmann - Bötzingen, Germany

copyright:

Copyright 2016-2017 Patrick Lehmann - Dresden, Germany

license:

Apache License, Version 2.0

Submodules

Classes

  • VHDLVersion: An enumeration for all possible version numbers for VHDL and VHDL-AMS.

  • IEEEFlavor: The IEEE VHDL library as a fixed set of predefined VHDL packages according to IEEE Std. 1076.

  • ObjectClass: An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).

  • DesignUnitKind: A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).

  • DependencyGraphVertexKind: A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.

  • DependencyGraphEdgeKind: A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.

  • ObjectGraphVertexKind: A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.

  • ObjectGraphEdgeKind: A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.

  • Design: A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

  • Library: A Library represents a VHDL library. It contains all primary and secondary design units.

  • Document: A Document represents a sourcefile. It contains primary and secondary design units.

Classes

class pyVHDLModel.VHDLVersion(*values)[source]

An enumeration for all possible version numbers for VHDL and VHDL-AMS.

A version can be given as integer or string and is represented as a unified enumeration value.

This enumeration supports compare operators.

Inheritance

Inheritance diagram of VHDLVersion

Any = -1

Any

VHDL87 = 87

VHDL-1987

VHDL93 = 93

VHDL-1993

AMS93 = 1993

VHDL-AMS-1993

AMS99 = 1999

VHDL-AMS-1999

VHDL2000 = 2000

VHDL-2000

VHDL2002 = 2002

VHDL-2002

VHDL2008 = 2008

VHDL-2008

AMS2017 = 2017

VHDL-AMS-2017

VHDL2019 = 2019

VHDL-2019

Latest = 10000

Latest VHDL (2019)

__VERSION_MAPPINGS__: Dict[int | str, Enum] = {'00': 2000, '02': 2002, '08': 2008, '17': 2017, '19': 2019, '1987': 87, '1993': 1993, '1999': 1999, '2000': 2000, '2002': 2002, '2008': 2008, '2017': 2017, '2019': 2019, '87': 87, '93': 93, '99': 1999, 'Any': Any, 'Latest': Latest, -1: Any, 0: 2000, 10000: Latest, 17: 2017, 19: 2019, 1987: 87, 1993: 1993, 1999: 1999, 2: 2002, 2000: 2000, 2002: 2002, 2008: 2008, 2017: 2017, 2019: 2019, 8: 2008, 87: 87, 93: 93, 99: 1999}

Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.

__init__(*_)[source]

Patch the embedded MAP dictionary

Return type:

None

classmethod Parse(value)[source]

Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.

Parameters:

value (int | str) – VHDL/VHDL-AMS year code.

Return type:

VHDLVersion

Returns:

Enumeration value.

Raises:

ValueError – If the year code is not recognized.

__lt__()[source]

Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is less than the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__le__()[source]

Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is less or equal than the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__gt__()[source]

Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is greater than the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__ge__()[source]

Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is greater or equal than the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__ne__()[source]

Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is unequal to the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__eq__()[source]

Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.

Parameters:

other (VHDLVersion) – Parameter to compare against.

Return type:

bool

Returns:

True if version is equal to the second operand.

Raises:

TypeError – If parameter other is not of type VHDLVersion.

__hash__()[source]

Return the hash of the VHDL version using the underlying version number.

Note

Any compares equal to every other member (see __eq__()), which no hash value can satisfy simultaneously for all members without collapsing every member to the same hash. This implementation hashes by self.value, which is internally consistent for all comparisons except those involving Any - avoid using Any as a dict key or set member.

Return type:

int

Returns:

Hash value of the underlying VHDL version number.

property IsVHDL: bool

Check if the version is a VHDL (not VHDL-AMS) version.

Returns:

True, if the version is a VHDL version.

property IsAMS: bool

Check if the version is a VHDL-AMS (not VHDL) version.

Returns:

True, if the version is a VHDL-AMS version.

__str__()[source]

Formats the VHDL version to pattern VHDL'xx or in case of VHDL-AMS to VHDL-AMS'xx.

Return type:

str

Returns:

Formatted VHDL/VHDL-AMS version.

__repr__()[source]

Formats the VHDL/VHDL-AMS version to pattern xxxx.

Return type:

str

Returns:

Formatted VHDL/VHDL-AMS version.

classmethod __contains__(value)

Return True if value is in cls.

value is in cls if: 1) value is a member of cls, or 2) value is the value of one of the cls’s members. 3) value is a pseudo-member (flags)

classmethod __getitem__(name)

Return the member matching name.

classmethod __iter__()

Return members in definition order.

classmethod __len__()

Return the number of members (no aliases)

class pyVHDLModel.IEEEFlavor(*values)[source]

The IEEE VHDL library as a fixed set of predefined VHDL packages according to IEEE Std. 1076.

Nonetheless, some vendors decided to sneak in additional packages into the IEEE namespace.
Supported flavors are:

  • Synopsys

  • MentorGraphics

In addition, IEEE Std. 1076.X extensions can be loaded.
Supported extensions are:

  • WithVITAL - IEEE Std. 1076.4

Inheritance

Inheritance diagram of IEEEFlavor

Unknown = 0

Unknown IEEE flavor

IEEE = 1

IEEE Std. 1076 compliant list of IEEE packages.

Synopsys = 2

Additional packages created by Synopsys are visible within the IEEE library.

MentorGraphics = 4

Additional packages created by Mentor Graphics are visible within the IEEE library.

WithVITAL = 32

Additionally load IEEE Std 1076.4 VITAL packages. (VITAL = VHDL Initiative Towards ASIC Libraries)

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.ObjectClass(*values)[source]

An ObjectClass is an enumeration and represents an object’s class (constant, signal, …).

In case no object class is defined, Default is used, so the object class is inferred from context.

Inheritance

Inheritance diagram of ObjectClass

Default = 0

Object class not defined, thus it’s context dependent.

Constant = 1

Constant

Variable = 2

Variable

Signal = 3

Signal

File = 4

File

Type = 5

Type

Procedure = 6

Procedure

Function = 7

Function

__str__()[source]

Formats the object class.

Return type:

str

Returns:

Formatted object class.

classmethod __contains__(value)

Return True if value is in cls.

value is in cls if: 1) value is a member of cls, or 2) value is the value of one of the cls’s members. 3) value is a pseudo-member (flags)

classmethod __getitem__(name)

Return the member matching name.

classmethod __iter__()

Return members in definition order.

classmethod __len__()

Return the number of members (no aliases)

class pyVHDLModel.DesignUnitKind(*values)[source]

A DesignUnitKind is an enumeration and represents the kind of design unit (Entity, Architecture, …).

Inheritance

Inheritance diagram of DesignUnitKind

Context = 1

Context

Package = 2

Package

PackageBody = 4

Package Body

Entity = 8

Entity

Architecture = 16

Architecture

Configuration = 32

Configuration

Primary = 43

List of primary design units.

Secondary = 20

List of secondary design units.

WithContext = 62

List of design units with a context.

WithDeclaredItems = 30

List of design units having a declaration region.

All = 63

List of all design units.

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.DependencyGraphVertexKind(*values)[source]

A DependencyGraphVertexKind is an enumeration and represents the kind of vertex in the dependency graph.

Inheritance

Inheritance diagram of DependencyGraphVertexKind

Document = 1

A document (VHDL source file).

Library = 2

A VHDL library.

Context = 4

A context design unit.

Package = 8

A package design unit.

PackageBody = 16

A package body design unit.

Entity = 32

A entity design unit.

Architecture = 64

A architecture design unit.

Component = 128

A VHDL component.

Configuration = 256

A configuration design unit.

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.DependencyGraphEdgeKind(*values)[source]

A DependencyGraphEdgeKind is an enumeration and represents the kind of edge in the dependency graph.

Inheritance

Inheritance diagram of DependencyGraphEdgeKind

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.ObjectGraphVertexKind(*values)[source]

A ObjectGraphVertexKind is an enumeration and represents the kind of vertex in the object graph.

Inheritance

Inheritance diagram of ObjectGraphVertexKind

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.ObjectGraphEdgeKind(*values)[source]

A ObjectGraphEdgeKind is an enumeration and represents the kind of edge in the object graph.

Inheritance

Inheritance diagram of ObjectGraphEdgeKind

static _generate_next_value_(name, start, count, last_values)

Generate the next value when not given.

name: the name of the member start: the initial start value or None count: the number of existing members last_values: the last value assigned or None

_numeric_repr_(obj, /)

Return the canonical string representation of the object.

For many object types, including most builtins, eval(repr(obj)) == obj.

classmethod _iter_member_by_value_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_(value)

Extract all members from the value in definition (i.e. increasing value) order.

classmethod _iter_member_by_def_(value)

Extract all members from the value in definition order.

classmethod _missing_(value)

Create a composite member containing all canonical members present in value.

If non-member values are present, result depends on _boundary_ setting.

__contains__(other)

Returns True if self has at least the same flags set as other.

__iter__()

Returns flags in definition order.

__len__()

Return the number of members (no aliases)

__repr__()

Return repr(self).

__str__()

Return str(self).

__bool__()

classes/types should always be True.

__or__(other)

Return self|value.

__ror__(other)

Return value|self.

__new__(value)
classmethod __getitem__(name)

Return the member matching name.

class pyVHDLModel.Design(name=None, allowBlackbox=False)[source]

A Design represents set of VHDL libraries as well as all loaded and analysed source files (see Document).

It’s the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see Library). When the design is analysed (see Analyze()), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design’s compile order and hierarchy can be iterated. As a second result, the design’s top-level is identified and referenced from the design (see TopLevel).

The design contains references to the following graphs:

Inheritance

Inheritance diagram of Design

Parameters:

  • name (str | None)

  • allowBlackbox (bool)

_allowBlackbox: bool

Allow blackboxes after linking the design.

__init__(name=None, allowBlackbox=False)[source]

Initialize a VHDL design.

Parameters:

  • name (str | None) – Name of the design.

  • allowBlackbox (bool) – Specify if blackboxes are allowed in this design.

Return type:

None

_name: str | None

Name of the design.

_libraries: Dict[str, Library]

List of all libraries defined for a design.

_documents: List[Document]

List of all documents loaded for a design.

_compileOrderGraph: Graph[None, None, None, None, None, None, None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

A graph derived from dependency graph containing the order of documents for compilation.

_dependencyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]

The graph of all dependencies in the designs.

_hierarchyGraph: Graph[None, None, None, None, None, None, None, None, str, DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]

A graph derived from dependency graph containing the design hierarchy.

_objectGraph: Graph[None, None, None, None, None, None, None, None, str, Obj, None, None, None, None, None, None, None, None, None, None, None, None, None]

The graph of all types and objects in the design.

_toplevel: Entity | Configuration

When computed, the toplevel design unit is cached in this field.

property Name: str | None

Read-only property to access the design’s name (_name).

Returns:

The name of the design.

property Libraries: Dict[str, Library]

Read-only property to access the dictionary of library names and VHDL libraries (_libraries).

Returns:

A dictionary of library names and VHDL libraries.

property Documents: List[Document]

Read-only property to access the list of all documents (VHDL source files) loaded for this design (_documents).

Returns:

A list of all documents.

property CompileOrderGraph: Graph

Read-only property to access the compile-order graph (_compileOrderGraph).

Returns:

Reference to the compile-order graph.

property DependencyGraph: Graph

Read-only property to access the dependency graph (_dependencyGraph).

Returns:

Reference to the dependency graph.

property HierarchyGraph: Graph

Read-only property to access the hierarchy graph (_hierarchyGraph).

Returns:

Reference to the hierarchy graph.

property ObjectGraph: Graph

Read-only property to access the object graph (_objectGraph).

Returns:

Reference to the object graph.

property TopLevel: Entity | Configuration

Read-only property to access the design’s top-level (_toplevel).

When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field toplevel is added to _hierarchyGraph referencing that single element. In addition, the result is cached in _toplevel.

Returns:

Reference to the design’s top-level.

Raises:
LoadStdLibrary()[source]

Load the predefined VHDL library std into the design.

This will create a virtual source code file std.vhdl and register VHDL design units of library std to that file.

Return type:

Library

Returns:

The library object of library std.

LoadIEEELibrary(flavor=None)[source]

Load the predefined VHDL library ieee into the design.

This will create a virtual source code file ieee.vhdl and register VHDL design units of library ieee to that file.

Parameters:

flavor (IEEEFlavor | None) – Select the IEEE library flavor: IEEE, Synopsys, MentorGraphics.

Return type:

Library

Returns:

The library object of library ieee.

AddLibrary(library)[source]

Add a VHDL library to the design.

Ensure the libraries name doesn’t collide with existing libraries in the design.
If ok, set the libraries parent reference to the design.

Parameters:

library (Library) – Library object to loaded.

Raises:
Return type:

None

GetLibrary(libraryName)[source]

Return an (existing) VHDL library object of name libraryName.

If the requested VHDL library doesn’t exist, a new VHDL library with that name will be created.

Parameters:

libraryName (str) – Name of the requested VHDL library.

Return type:

Library

Returns:

The VHDL library object.

AddDocument(document, library)[source]

Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.

Algorithm

  1. Iterate all entities in the document

    1. Check if entity name might exist in target library.

    2. Add entity to library and update library membership.

  2. Iterate all architectures in the document

    1. Check if architecture name might exist in target library.

    2. Add architecture to library and update library membership.

  3. Iterate all packages in the document

    1. Check if package name might exist in target library.

    2. Add package to library and update library membership.

  4. Iterate all package bodies in the document

    1. Check if package body name might exist in target library.

    2. Add package body to library and update library membership.

  5. Iterate all configurations in the document

    1. Check if configuration name might exist in target library.

    2. Add configuration to library and update library membership.

  6. Iterate all contexts in the document

    1. Check if context name might exist in target library.

    2. Add context to library and update library membership.

Parameters:

  • document (Document) – The VHDL source code file.

  • library (Library) – The VHDL library used to register the embedded design units to.

Raises:
Return type:

None

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the design.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

  1. Iterate all VHDL libraries.

    1. Iterate all contexts in that library.

    2. Iterate all packages in that library.

    3. Iterate all package bodies in that library.

    4. Iterate all entites in that library.

    5. Iterate all architectures in that library.

    6. Iterate all configurations in that library.

Parameters:

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

Return type:

Generator[DesignUnit]

Returns:

A generator to iterate all matched design units in the design.

See also

pyVHDLModel.Library.IterateDesignUnits()

Iterate all design units in the library.

pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

Analyze()[source]

Analyze the whole design.

Algorithm

  1. Analyze dependencies of design units.
    This will also yield the design hierarchy and the compiler order.

  2. Analyze dependencies of types and objects.

See also

AnalyzeDependencies()

Analyze the dependencies of design units.

AnalyzeObjects()

Analyze the dependencies of types and objects.

Return type:

None

AnalyzeDependencies()[source]

Analyze the dependencies of design units.

Algorithm

  1. Create all vertices of the dependency graph by iterating all design units in all libraries.
    → CreateDependencyGraph()

  2. Create the compile order graph.
    → CreateCompileOrderGraph()

  3. Index all packages.
    → IndexPackages()

  4. Index all architectures.
    → IndexArchitectures()

  5. Link all contexts
    → LinkContexts()

  6. Link all architectures.
    → LinkArchitectures()

  7. Link all package bodies.
    → LinkPackageBodies()

  8. Link all package instances.
    → LinkPackageInstances()

  9. Link all library references.
    → LinkLibraryReferences()

  10. Link all package references.
    → LinkPackageReferences()

  11. Link all context references.
    → LinkContextReferences()

  12. Link all components.
    → LinkComponents()

  13. Link all instantiations.
    → LinkInstantiations()

  14. Create the hierarchy graph.
    → CreateHierarchyGraph()

  15. Compute the compile order.
    → ComputeCompileOrder()

Return type:

None

AnalyzeObjects()[source]

Analyze the dependencies of types and objects.

Algorithm

  1. Index all entities.
    → IndexEntities()

  2. Index all package bodies.
    → IndexPackageBodies()

  3. Import objects.
    → ImportObjects()

  4. Create the type and object graph.
    → CreateTypeAndObjectGraph()

Return type:

None

CreateDependencyGraph()[source]

Create all vertices of the dependency graph by iterating all design units in all libraries.

This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods.
See AnalyzeDependencies() for these methods and their algorithmic order.

Each vertex has the following properties:

  • The vertex’ ID is the design unit’s identifier.

  • The vertex’ value references the design unit.

  • A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.

  • A key-value-pair called predefined denotes if the referenced design unit is a predefined language entity.

Algorithm

  1. Iterate all libraries in the design.

    • Create a vertex for that library and reference the library by the vertex’ value field.
      In return, set the library’s _dependencyVertex field to reference the created vertex.

    1. Iterate all contexts in that library.

      • Create a vertex for that context and reference the context by the vertex’ value field.
        In return, set the context’s _dependencyVertex field to reference the created vertex.

    2. Iterate all packages in that library.

      • Create a vertex for that package and reference the package by the vertex’ value field.
        In return, set the package’s _dependencyVertex field to reference the created vertex.

    3. Iterate all package bodies in that library.

      • Create a vertex for that package body and reference the package body by the vertex’ value field.
        In return, set the package body’s _dependencyVertex field to reference the created vertex.

    4. Iterate all entities in that library.

      • Create a vertex for that entity and reference the entity by the vertex’ value field.
        In return, set the entity’s _dependencyVertex field to reference the created vertex.

    5. Iterate all architectures in that library.

      • Create a vertex for that architecture and reference the architecture by the vertex’ value field.
        In return, set the architecture’s _dependencyVertex field to reference the created vertex.

    6. Iterate all configurations in that library.

      • Create a vertex for that configuration and reference the configuration by the vertex’ value field.
        In return, set the configuration’s _dependencyVertex field to reference the created vertex.

Return type:

None

CreateCompileOrderGraph()[source]

Create a compile-order graph with bidirectional references to the dependency graph.

Add vertices representing a document (VHDL source file) to the dependency graph. Each “document” vertex in dependency graph is copied into the compile-order graph and bidirectionally referenced.

In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in document relationship.

Each added vertex has the following properties:

  • The vertex’ ID is the document’s filename.

  • The vertex’ value references the document.

  • A key-value-pair called kind denotes the vertex’s kind as an enumeration value of type DependencyGraphVertexKind.

  • A key-value-pair called predefined does not exist.

Algorithm

  1. Iterate all documents in the design.

    • Create a vertex for that document and reference the document by the vertex’ value field.
      In return, set the documents’s _dependencyVertex field to reference the created vertex.

    • Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally.
      In addition, set the documents’s _dependencyVertex field to reference the copied vertex.

      • Add a key-value-pair called compileOrderVertex to the dependency graph’s vertex.

      • Add a key-value-pair called dependencyVertex to the compiler-order graph’s vertex.

    1. Iterate the documents design units and create an edge from the design unit’s corresponding dependency vertex to the documents corresponding dependency vertex. This expresses a “design unit is located in document” relation.

      • Add a key-value-pair called kind` denoting the edge’s kind as an enumeration value of type DependencyGraphEdgeKind.

Return type:

None

LinkContexts()[source]

Resolves and links all items (library clauses, use clauses and nested context references) in contexts.

It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By default, the working library is implicitly referenced in _referencedLibraries. In addition, a new empty dictionary is created in _referencedPackages and _referencedContexts for that working library.

At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each referenced library an entry in _referencedLibraries is generated and new empty dictionaries in _referencedPackages and _referencedContexts for that working library. In addition, a vertex in the dependency graph is added for that relationship.

At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each referenced package,

Return type:

None

LinkArchitectures()[source]

Link all architectures to corresponding entities in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all architecture groups (grouped per entity symbol’s name). → pyVHDLModel.Library.LinkArchitectures()

      • Check if entity symbol’s name exists as an entity in this library.

      1. For each architecture in the same architecture group:

See also

LinkPackageBodies()

Link all package bodies to corresponding packages in all libraries.

LinkPackageInstances()

Link all package instances to corresponding generic packages in all libraries.

Return type:

None

LinkPackageBodies()[source]

Link all package bodies to corresponding packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all package bodies. → pyVHDLModel.Library.LinkPackageBodies()

      • Check if package body symbol’s name exists as a package in this library.

      • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

      • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

      • Set parent namespace of package body’s namespace to the package’s namespace.

      • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

See also

LinkArchitectures()

Link all architectures to corresponding entities in all libraries.

LinkPackageInstances()

Link all package instances to corresponding generic packages in all libraries.

Return type:

None

LinkPackageInstances()[source]

Link all package instances to corresponding generic packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all package instances. → pyVHDLModel.Library.LinkPackageInstances()

Todo

  • Check if package instance’s symbol’s name exists as a generic package in this library.

  • Add generic package to package instance pyVHDLModel.DesignUnit.Package._packageBody.

  • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

  • Set parent namespace of package body’s namespace to the package’s namespace.

  • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

See also

LinkArchitectures()

Link all architectures to corresponding entities in all libraries.

LinkPackageBodies()

Link all package bodies to corresponding packages in all libraries.

Return type:

None

LinkLibraryReferences()[source]

Link all library references (library clause) to the matching VHDL library.

Algorithm

  1. Iterate all design units with contexts:

    • If the design unit is a primary unit:

      1. Iterate all library identifiers in DEFAULT_LIBRARIES (std):

        • Get the referenced library by name from the design.

        • Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.

        • Add an empty dictionary in the design unit’s _referencedPackages dictionary.

        • Add an empty dictionary in the design unit’s _referencedContexts dictionary.

        • Add an edge in the dependency graph from design unit to the referenced library.

      2. Get the design unit’s library:

        • Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.

        • Add an empty dictionary in the design unit’s _referencedPackages dictionary.

        • Add an empty dictionary in the design unit’s _referencedContexts dictionary.

        • Add an edge in the dependency graph from design unit to the referenced library.

    • If the design unit is a secondary unit:

      • If design unit is an architecture, get the corresponding entity’s referenced libraries.

      • If design unit is a package body, get the corresponding package’s referenced libraries.

      • Otherwise, raise an exception

      For every referenced library create new dictionary entries in the design unit’s _referencedLibraries.

  2. Iterate every library reference (library clause) in the design unit:

    • Iterate every library symbol within the library reference:

      • Get the library identifier from the symbol.

      • Continue the inner loop, if identifier is work.

      • Get the referenced library from the design or raise an exception.

      • Update the library symbol’s target with the referenced library.

      • Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.

      • Add an empty dictionary in the design unit’s _referencedPackages dictionary.

      • Add an empty dictionary in the design unit’s _referencedContexts dictionary.

      • Add an edge in the dependency graph from design unit to the referenced library.

See also

LinkPackageReferences()

Link use clause.

LinkContextReferences()

Link context clause.

AnalyzeDependencies()

Analyze dependencies and link relations.

Return type:

None

LinkPackageReferences()[source]

Link all package references (use clause) to the matching packages.

Algorithm

  1. Iterate all design units with contexts:

    • If the design unit is a primary unit:

      • If primary unit isn’t package std.standard:

        1. Iterate all library, packages tuples in DEFAULT_PACKAGES (std: [standard]):

          • Raise an exception, if library isn’t listed in design unit’s _referencedLibraries.

          • For every package in packages:

            • Get the referenced package by library name and package name from the design.

            • Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.

            • Add an edge in the dependency graph from design unit to the referenced package.

    • If the design unit is a secondary unit:

      • If design unit is an architecture, get the corresponding entity’s referenced packages.

      • If design unit is a package body, get the corresponding package’s referenced packages.

      • Otherwise, raise an exception

      For every referenced package create new dictionary entries in the design unit’s _referencedPackages.

  2. Iterate every package reference (use clause) in the design unit:

    • Iterate every package symbol within the package reference:

      1. Get the library identifier from the symbol.

      2. Get the package identifier from the symbol.

      3. Resolve library:

        • If library name is work, get library from design unit.

        • If library name is not in design unit’s _referencedLibraries, raise an exception.

        • Otherwise, lookup library by name in design.

      4. Resolve package:

        • Lookup package by name in library.

      5. Update design unit:

        • Update the package symbol’s target with the referenced package.

        • Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.

        • Add an edge in the dependency graph from design unit to the referenced package.

      6. Import public package members.

        • If package symbol is a AllPackageMembersReferenceSymbol:

          • Iterate all components within the referenced package and add entries for each component in the design unit’s _namespace.

          Todo

          Other elements are not implemented.

        • If package symbol is a PackageMemberReferenceSymbol

          Todo

          Not implemented.

        • Otherwise, raise an exception.

See also

LinkLibraryReferences()

Link library clause.

LinkContextReferences()

Link context clause.

AnalyzeDependencies()

Analyze dependencies and link relations.

Return type:

None

LinkContextReferences()[source]

Link all context references (context clause) to the matching context.

Algorithm

  1. Iterate all design units:

    • Iterate all context references in the design unit:

      • Iterate each context symbol within the context reference.

        1. Get the library identifier from the symbol.

        2. Get the context identifier from the symbol.

        3. Resolve library:

          • If library name is work, get library from design unit.

          • If library name is not in design unit’s _referencedLibraries, raise an exception.

          • Otherwise, lookup library by name in design.

        4. Resolve context:

          • Lookup context by name in library.

        5. Update design unit:

          • Update the context symbol’s target with the referenced context.

          • Add an entry in the design unit’s _referencedContexts dictionary referencing the referenced context.

          • Add an edge in the dependency graph from design unit to the referenced context.

  2. Iterate all context vertices in the dependency graph (_dependencyGraph) in topological order:

    • Get the context from the context vertex.

    • Iterate all predecessor vertices (design unit vertices) of the context vertex:

      1. Get the design unit from design unit vertex.

      2. Iterate referenced libraries of the context:

        • Add an entry in the design unit’s _referencedLibraries dictionary referencing the referenced library.

        • Add an empty dictionary in the design unit’s _referencedPackages dictionary.

      3. Iterate referenced packages of the context:

        • Raise an exception if package name is already listed in _referencedPackages.

        • Add an entry in the design unit’s _referencedPackages dictionary referencing the referenced package.

See also

LinkLibraryReferences()

Link library clause.

LinkPackageReferences()

Link use clause.

AnalyzeDependencies()

Analyze dependencies and link relations.

Return type:

None

LinkComponents()[source]

Link components to matching entities found in same VHDL library.

Algorithm

  1. Iterate all design units with component declarations (packages and architectures):

    1. Iterate all component declarations in a package or architecture:

      • Check if an entity with matching name can be found in the VHDL library the package is declared within. If found, set the component’s entity reference to that entity, otherwise check if blackboxes are allowed for that component. If so, mark the component as a blackbox, otherwise, raise an exception.

    2. Iterate concurrent statements with declaration regions (block statements, generate statements) if the design unit is an architecture:

      • If the statement is an IfGenerateStatement:

        1. Iterate declared components in the IfGenerateBranch.

        2. Iterate declared components in each ElIfGenerateBranch.

        3. Iterate declared components in the ElseGenerateBranch if it exists.

      • If the statement is an ForGenerateStatement:

        1. Iterate declared components.

      • If the statement is an CaseGenerateStatement:

        1. Iterate declared components.

        2. Iterate

See also

LinkInstantiations()

Link instantiations to components and entities.

AnalyzeDependencies()

Analyze dependencies in a design (calls this method).

Return type:

None

IndexPackages()[source]

Index all declared items in all packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all packages
      → pyVHDLModel.Library.IndexPackages()

See also

IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

IndexEntities()

Index all declared items in all entities in all libraries.

IndexArchitectures()

Index all declared items in all architectures in all libraries.

Return type:

None

IndexPackageBodies()[source]

Index all declared items in all packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all packages
      → pyVHDLModel.Library.IndexPackageBodies()

See also

IndexPackages()

Index all declared items in all packages in all libraries.

IndexEntities()

Index all declared items in all entities in all libraries.

IndexArchitectures()

Index all declared items in all architectures in all libraries.

Return type:

None

IndexEntities()[source]

Index all declared items in all packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all packages
      → pyVHDLModel.Library.IndexEntities()

See also

IndexPackages()

Index all declared items in all packages in all libraries.

IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

IndexArchitectures()

Index all declared items in all architectures in all libraries.

Return type:

None

IndexArchitectures()[source]

Index all declared items in all packages in all libraries.

Algorithm

  1. Iterate all libraries:

    1. Iterate all packages
      → pyVHDLModel.Library.IndexArchitectures()

See also

IndexPackages()

Index all declared items in all packages in all libraries.

IndexPackageBodies()

Index all declared items in all package bodies in all libraries.

IndexEntities()

Index all declared items in all entities in all libraries.

Return type:

None

CreateHierarchyGraph()[source]

Create the hierarchy graph from dependency graph.

Algorithm

  1. Iterate all vertices corresponding to entities and architectures in the dependency graph:

    • Copy these vertices to the hierarchy graph and create a bidirectional linking.
      In addition, set the referenced design unit’s _hierarchyVertex field to reference the copied vertex.

      • Add a key-value-pair called hierarchyVertex to the dependency graph’s vertex.

      • Add a key-value-pair called dependencyVertex to the hierarchy graph’s vertex.

  2. Iterate all architectures …

    Todo

    Design::CreateHierarchyGraph describe algorithm

    1. Iterate all outbound edges

      Todo

      Design::CreateHierarchyGraph describe algorithm

Return type:

None

IterateDocumentsInCompileOrder()[source]

Iterate all document in compile-order.

Algorithm

  • Check if compile-order graph was populated with vertices and its vertices are linked by edges.

  1. Iterate compile-order graph in topological order.
    pyTooling.Graph.Graph.IterateTopologically()

    • yield the compiler-order vertex’ referenced document.

Return type:

Generator[Document]

Returns:

A generator to iterate all documents in compile-order in the design.

Raises:

VHDLModelException – If compile-order was not computed.

See also

Todo

missing text

pyVHDLModel.Design.ComputeCompileOrder()

__repr__()[source]

Formats a representation of the design.

Format: Document: 'my_design'

Return type:

str

Returns:

String representation of the design.

__str__()

Formats a representation of the design.

Format: Document: 'my_design'

Return type:

str

Returns:

String representation of the design.

property AllowBlackbox: bool

Property to return whether a design supports blackboxes, inherited from the parent if not set locally (_allowBlackbox).

Algorithm

  1. If allow blackbox property is locally set, return the local value,

  2. Otherwise, return allow blackbox value from parent object.

Returns:

True, if blackboxes are allowed.

Raises:

VHDLModelException – If neither a local value is set nor a parent object is available to inherit the value from.

Setter accepts:

bool | None

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:

type (Type) – Class (type) of the ancestor to find.

Return type:

ModelEntity

Returns:

The closest ancestor of the requested type.

Raises:

VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

classmethod GetMethodsWithAttributes(predicate=None)
Parameters:

predicate (TAttr | Iterable[TAttr] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

  • ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.

  • ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__getstate__()

Helper for pickle.

Return type:

Dict[str, Any]

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Library(identifier, documentation=None, allowBlackbox=None, parent=None)[source]

A Library represents a VHDL library. It contains all primary and secondary design units.

See also

Inheritance

Inheritance diagram of Library

Parameters:
_allowBlackbox: bool | None

Allow blackboxes for components in this library.

__init__(identifier, documentation=None, allowBlackbox=None, parent=None)[source]

Initialize a VHDL library.

Parameters:

  • identifier (str) – Name of the VHDL library.

  • documentation (str | None) – Documentation of this VHDL library, if the caller has one to supply.

  • allowBlackbox (bool | None) – Specify if blackboxes are allowed in this design.

  • parent (ModelEntity | None) – The parent model entity (design) of this VHDL library.

Return type:

None

_contexts: Dict[str, Context]

Dictionary of all contexts defined in a library.

_configurations: Dict[str, Configuration]

Dictionary of all configurations defined in a library.

_entities: Dict[str, Entity]

Dictionary of all entities defined in a library.

_architectures: Dict[str, Dict[str, Architecture]]

Dictionary of all architectures defined in a library.

_packages: Dict[str, Package]

Dictionary of all packages defined in a library.

_packageBodies: Dict[str, PackageBody]

Dictionary of all package bodies defined in a library.

_dependencyVertex: Vertex[None, None, str, Library | DesignUnit, None, None, None, None, None, None, None, None, None, None, None, None, None]

Reference to the vertex in the dependency graph representing the library.
This reference is set by CreateDependencyGraph().

property Documentation: str | None

Property to access the library’s documentation (_documentation).

Hint

Unlike every other documented entity, a library’s documentation cannot come from VHDL source: the language has no library declaration to attach a comment to. It is therefore settable, so a caller can supply one from elsewhere - a compile-order file, a project description, …

Returns:

Associated documentation of this VHDL library.

property Contexts: Dict[str, Context]

Read-only property to access the dictionary of all context declarations in this library (_contexts).

Returns:

Dictionary of all contexts, indexed by normalized identifier.

property Configurations: Dict[str, Configuration]

Read-only property to access the dictionary of all configuration declarations in this library (_configurations).

Returns:

Dictionary of all configurations, indexed by normalized identifier.

property Entities: Dict[str, Entity]

Read-only property to access the dictionary of all entity declarations in this library (_entities).

Returns:

Dictionary of all entities, indexed by normalized identifier.

property Architectures: Dict[str, Dict[str, Architecture]]

Read-only property to access the dictionary of all architecture declarations in this library (_architectures).

Returns:

Dictionary of all architectures, indexed by normalized entity identifier, then by normalized architecture identifier.

property Packages: Dict[str, Package]

Read-only property to access the dictionary of all package declarations in this library (_packages).

Returns:

Dictionary of all packages, indexed by normalized identifier.

property PackageBodies: Dict[str, PackageBody]

Read-only property to access the dictionary of all package body declarations in this library (_packageBodies).

Returns:

Dictionary of all package bodies, indexed by normalized identifier.

property DependencyVertex: Vertex

Read-only property to access the corresponding dependency vertex (_dependencyVertex).

The dependency vertex references this library by its value field.

Returns:

The corresponding dependency vertex.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the library.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

  1. Iterate all contexts in that library.

  2. Iterate all packages in that library.

  3. Iterate all package bodies in that library.

  4. Iterate all entities in that library.

  5. Iterate all architectures in that library.

  6. Iterate all configurations in that library.

Parameters:

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

Return type:

Generator[DesignUnit]

Returns:

A generator to iterate all matched design units in the library.

See also

pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

pyVHDLModel.Document.IterateDesignUnits()

Iterate all design units in the document.

LinkArchitectures()[source]

Link all architectures to corresponding entities.

Algorithm

  1. Iterate all architecture groups (grouped per entity symbol’s name).

    • Check if entity symbol’s name exists as an entity in this library.

    1. For each architecture in the same architecture group:

Raises:
Return type:

None

See also

LinkPackageBodies()

Link all package bodies to corresponding packages.

LinkPackageInstances()

Link all package instances to corresponding generic packages.

LinkPackageBodies()[source]

Link all package bodies to corresponding packages.

Algorithm

  1. Iterate all package bodies.

    • Check if package body symbol’s name exists as a package in this library.

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

    • Set parent namespace of package body’s namespace to the package’s namespace.

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

Raises:

VHDLModelException – If package name doesn’t exist.

Return type:

None

See also

LinkArchitectures()

Link all architectures to corresponding entities.

LinkPackageInstances()

Link all package instances to corresponding generic packages.

LinkPackageInstances()[source]

Link all package instances to corresponding generic packages.

Algorithm

  1. Iterate all package instances.

    Todo

    • Check if package body symbol’s name exists as a package in this library.

    • Add package body to package pyVHDLModel.DesignUnit.Package._packageBody.

    • Assign found package to package body’s package symbol pyVHDLModel.DesignUnit.PackageBody._package

    • Set parent namespace of package body’s namespace to the package’s namespace.

    • Add an edge in the dependency graph from the package body’s corresponding dependency vertex to the package’s corresponding dependency vertex.

Raises:

VHDLModelException – If generic package name doesn’t exist.

Return type:

None

See also

LinkArchitectures()

Link all architectures to corresponding entities.

LinkPackageBodies()

Link all package bodies to corresponding packages.

IndexPackages()[source]

Index declared items in all packages.

Algorithm

  1. Iterate all packages:

See also

IndexPackageBodies()

Index all declared items in a package body.

IndexEntities()

Index all declared items in an entity.

IndexArchitectures()

Index all declared items in an architecture.

Return type:

None

IndexPackageBodies()[source]

Index declared items in all package bodies.

Algorithm

  1. Iterate all package bodies:

See also

IndexPackages()

Index all declared items in a package.

IndexEntities()

Index all declared items in an entity.

IndexArchitectures()

Index all declared items in an architecture.

Return type:

None

IndexEntities()[source]

Index declared items in all entities.

Algorithm

  1. Iterate all entities:

See also

IndexPackages()

Index all declared items in a package.

IndexPackageBodies()

Index all declared items in a package body.

IndexArchitectures()

Index all declared items in an architecture.

Return type:

None

IndexArchitectures()[source]

Index declared items in all architectures.

Algorithm

  1. Iterate all architectures:

See also

IndexPackages()

Index all declared items in a package.

IndexPackageBodies()

Index all declared items in a package body.

IndexEntities()

Index all declared items in an entity.

Return type:

None

__repr__()[source]

Formats a representation of the library.

Format: Library: 'my_library'

Return type:

str

Returns:

String representation of the library.

__str__()

Formats a representation of the library.

Format: Library: 'my_library'

Return type:

str

Returns:

String representation of the library.

_identifier: str

The identifier of a model entity.

_normalizedIdentifier: str

The normalized (lower case) identifier of a model entity.

_documentation: str | None

The associated documentation of a model entity.

property AllowBlackbox: bool

Property to return whether a design supports blackboxes, inherited from the parent if not set locally (_allowBlackbox).

Algorithm

  1. If allow blackbox property is locally set, return the local value,

  2. Otherwise, return allow blackbox value from parent object.

Returns:

True, if blackboxes are allowed.

Raises:

VHDLModelException – If neither a local value is set nor a parent object is available to inherit the value from.

Setter accepts:

bool | None

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:

type (Type) – Class (type) of the ancestor to find.

Return type:

ModelEntity

Returns:

The closest ancestor of the requested type.

Raises:

VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

classmethod GetMethodsWithAttributes(predicate=None)
Parameters:

predicate (TAttr | Iterable[TAttr] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

  • ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.

  • ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

property Identifier: str

Read-only property to access the model entity’s identifier (_identifier).

Returns:

Name of a model entity.

property NormalizedIdentifier: str

Read-only property to access the model entity’s normalized identifier (_normalizedIdentifier).

Returns:

Normalized name of a model entity.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__getstate__()

Helper for pickle.

Return type:

Dict[str, Any]

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Document(path, documentation=None, vhdlVersion=2008, library=None, parent=None)[source]

A Document represents a sourcefile. It contains primary and secondary design units.

Inheritance

Inheritance diagram of Document

Parameters:

  • path (<pyTooling.Decorators.readonly object at 0x725dd2b05450>)

  • documentation (str | None)

  • vhdlVersion (<pyTooling.Decorators.readonly object at 0x725dd2b054d0>)

  • library (<pyTooling.Decorators.readonly object at 0x725dd2b05550> | None)

  • parent (ModelEntity | None)

__init__(path, documentation=None, vhdlVersion=2008, library=None, parent=None)[source]

Initializes a VHDL document.

Parameters:

  • path (readonly) – Path to the document. None if in-memory document.

  • documentation (str | None) – The documentation comment associated with this declaration.

  • vhdlVersion (readonly) – VHDL version used for analyzing this source file.

  • library (readonly | None) – VHDL library used for analyzing the source file’s content into.

  • parent (ModelEntity | None) – The parent model entity of this entity.

Return type:

None

_path: readonly

Path to the document. None if in-memory document.

_vhdlVersion: readonly

VHDL version used for analyzing this source file.

_library: readonly

VHDL library used for analyzing the source file’s content into.

_designUnits: List[DesignUnit]

List of all design units defined in a document.

_contexts: Dict[str, Context]

Dictionary of all contexts defined in a document.

_configurations: Dict[str, Configuration]

Dictionary of all configurations defined in a document.

_entities: Dict[str, Entity]

Dictionary of all entities defined in a document.

_architectures: Dict[str, Dict[str, Architecture]]

Dictionary of all architectures defined in a document.

_packages: Dict[str, Package]

Dictionary of all packages defined in a document.

_packageBodies: Dict[str, PackageBody]

Dictionary of all package bodies defined in a document.

_verificationUnits: Dict[str, VerificationUnit]

Dictionary of all PSL verification units defined in a document.

_verificationProperties: Dict[str, VerificationProperty]

Dictionary of all PSL verification properties defined in a document.

_documentation: str | None

The associated documentation of a model entity.

property Documentation: str | None

Read-only property to access the model entity’s documentation (_documentation).

Returns:

Associated documentation of a model entity.

GetAncestor(type)

Return the closest ancestor of the given type found by walking the parent chain upwards.

Iterates the parent chain - starting at this model entity - upwards (toward the root of the model) until an ancestor of the requested type is found.

Parameters:

type (Type) – Class (type) of the ancestor to find.

Return type:

ModelEntity

Returns:

The closest ancestor of the requested type.

Raises:

VHDLModelException – If the root of the model is reached without finding an ancestor of the requested type.

classmethod GetMethodsWithAttributes(predicate=None)
Parameters:

predicate (TAttr | Iterable[TAttr] | None) – An attribute class, an iterable of attribute classes, or None to accept every attribute.

Return type:

Dict[Callable, Tuple[Attribute, ...]]

Returns:

Dictionary of methods and the matching attributes attached to them.

Raises:

  • ValueError – If an element of parameter ‘predicate’ is not a sub-class of Attribute.

  • ValueError – If parameter ‘predicate’ is neither an attribute class nor an iterable of those.

property Parent: ModelEntity

Property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__getstate__()

Helper for pickle.

Return type:

Dict[str, Any]

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

_verificationModes: Dict[str, VerificationMode]

Dictionary of all PSL verification modes defined in a document.

_dependencyVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

Reference to the vertex in the dependency graph representing the document.
This reference is set by CreateCompileOrderGraph().

_compileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

Reference to the vertex in the compile-order graph representing the document.
This reference is set by CreateCompileOrderGraph().

_AddEntity(item)[source]

Add an entity to the document’s lists of design units.

Parameters:

item (Entity) – Entity object to be added to the document.

Raises:
Return type:

None

_AddArchitecture(item)[source]

Add an architecture to the document’s lists of design units.

Parameters:

item (Architecture) – Architecture object to be added to the document.

Raises:
Return type:

None

_AddPackage(item)[source]

Add a package to the document’s lists of design units.

Parameters:

item (Package) – Package object to be added to the document.

Raises:
Return type:

None

_AddPackageBody(item)[source]

Add a package body to the document’s lists of design units.

Parameters:

item (PackageBody) – Package body object to be added to the document.

Raises:
Return type:

None

_AddContext(item)[source]

Add a context to the document’s lists of design units.

Parameters:

item (Context) – Context object to be added to the document.

Raises:
Return type:

None

_AddConfiguration(item)[source]

Add a configuration to the document’s lists of design units.

Parameters:

item (Configuration) – Configuration object to be added to the document.

Raises:
Return type:

None

_AddDesignUnit(item)[source]

Add a design unit to the document’s lists of design units.

Parameters:

item (DesignUnit) – Configuration object to be added to the document.

Raises:
Return type:

None

property Path: readonly

Read-only property to access the document’s path (_path).

Returns:

The path of this document.

property VHDLVersion: readonly

Read-only property to access the document’s VHDL version (_vhdlVersion).

Returns:

VHDL version used to analyze this VHDL file.

property Library: readonly

Read-only property to access the document’s VHDL library (_library).

Returns:

VHDL library used to analyze the VHDL file’s design units into.

property DesignUnits: List[DesignUnit]

Read-only property to access a list of all design units declarations found in this document (_designUnits).

Returns:

List of all design units.

property Contexts: Dict[str, Context]

Read-only property to access the dictionary of all context declarations in this document (_contexts).

Returns:

Dictionary of all contexts, indexed by normalized identifier.

property Configurations: Dict[str, Configuration]

Read-only property to access the dictionary of all configuration declarations in this document (_configurations).

Returns:

Dictionary of all configurations, indexed by normalized identifier.

property Entities: Dict[str, Entity]

Read-only property to access the dictionary of all entity declarations in this document (_entities).

Returns:

Dictionary of all entities, indexed by normalized identifier.

property Architectures: Dict[str, Dict[str, Architecture]]

Read-only property to access the dictionary of all architecture declarations in this document (_architectures).

Returns:

Dictionary of all architectures, indexed by normalized entity identifier, then by normalized architecture identifier.

property Packages: Dict[str, Package]

Read-only property to access the dictionary of all package declarations in this document (_packages).

Returns:

Dictionary of all packages, indexed by normalized identifier.

property PackageBodies: Dict[str, PackageBody]

Read-only property to access the dictionary of all package body declarations in this document (_packageBodies).

Returns:

Dictionary of all package bodies, indexed by normalized identifier.

property VerificationUnits: Dict[str, VerificationUnit]

Read-only property to access the dictionary of all verification unit declarations in this document (_verificationUnits).

Returns:

Dictionary of all verification units, indexed by normalized identifier.

property VerificationProperties: Dict[str, VerificationProperty]

Read-only property to access the dictionary of all verification property declarations in this document (_verificationProperties).

Returns:

Dictionary of all verification properties, indexed by normalized identifier.

property VerificationModes: Dict[str, VerificationMode]

Read-only property to access the dictionary of all verification mode declarations in this document (_verificationModes).

Returns:

Dictionary of all verification mode declarations, indexed by normalized identifier.

property CompileOrderVertex: Vertex[None, None, None, Document, None, None, None, None, None, None, None, None, None, None, None, None, None]

Read-only property to access the corresponding compile-order vertex (_compileOrderVertex).

The compile-order vertex references this document by its value field.

Returns:

The corresponding compile-order vertex.

IterateDesignUnits(filter=<DesignUnitKind.All: 63>)[source]

Iterate all design units in the document.

A union of DesignUnitKind values can be given to filter the returned result for suitable design units.

Algorithm

  • If contexts are selected in the filter:

    1. Iterate all contexts in that library.

  • If packages are selected in the filter:

    1. Iterate all packages in that library.

  • If package bodies are selected in the filter:

    1. Iterate all package bodies in that library.

  • If entites are selected in the filter:

    1. Iterate all entites in that library.

  • If architectures are selected in the filter:

    1. Iterate all architectures in that library.

  • If configurations are selected in the filter:

    1. Iterate all configurations in that library.

Parameters:

filter (DesignUnitKind) – An enumeration with possibly multiple flags to filter the returned design units.

Return type:

Generator[DesignUnit]

Returns:

A generator to iterate all matched design units in the document.

See also

pyVHDLModel.Design.IterateDesignUnits()

Iterate all design units in the design.

pyVHDLModel.Library.IterateDesignUnits()

Iterate all design units in the library.

__repr__()[source]

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:

str

Returns:

String representation of the document.

__str__()

Formats a representation of the document.

Format: Document: 'path/to/file.vhdl'

Return type:

str

Returns:

String representation of the document.