pyVHDLModel.Base
This module contains parts of an abstract document language model for VHDL.
Base-classes for the VHDL language model.
Variables
Classes
Direction: An enumeration representing a direction in a range (toordownto).Mode: AModeis an enumeration. It represents the direction of data exchange (in,out, …) for objects inModelEntity:ModelEntityis the base-class for all classes in the VHDL language model, except for mixin classes (see multipleNamedEntityMixin: ANamedEntityMixinis a mixin class for all VHDL entities that have identifiers.MultipleNamedEntityMixin: AMultipleNamedEntityMixinis a mixin class for all VHDL entities that declare multiple instances at once byLabeledEntityMixin: ALabeledEntityMixinis a mixin class for all VHDL entities that can have labels.DocumentedEntityMixin: ADocumentedEntityMixinis a mixin class for all VHDL entities that can have an associated documentation.ConditionalMixin: AConditionalMixinis a mixin-class for all statements with a condition.BranchMixin: ABranchMixinis a mixin-class for all statements with branches.ConditionalBranchMixin: ABaseBranchis a mixin-class for all branch statements with a condition.IfBranchMixin: ABaseIfBranchis a mixin-class for all if-branches.ElsifBranchMixin: ABaseElsifBranchis a mixin-class for all elsif-branches.ElseBranchMixin: ABaseElseBranchis a mixin-class for all else-branches.ReportStatementMixin: AMixinReportStatementis a mixin-class for all report and assert statements.AssertStatementMixin: AMixinAssertStatementis a mixin-class for all assert statements.BaseChoice: AChoiceis a base-class for all choices.BaseCase: ACaseis a base-class for all cases.Range:ModelEntityis the base-class for all classes in the VHDL language model, except for mixin classes (see multipleWaveformElement:ModelEntityis the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
Variables
- pyVHDLModel.Base.ExpressionUnion
Represent a union type
E.g. for int | str
ForwardRef('BaseExpression') | ForwardRef('QualifiedExpression') | ForwardRef('FunctionCall') | ForwardRef('TypeConversion') | ForwardRef('Literal')
Classes
- class pyVHDLModel.Base.Direction(*values)[source]
An enumeration representing a direction in a range (
toordownto).Inheritance
- To = 0
Ascending direction
- DownTo = 1
Descending direction
- __str__()[source]
Formats the direction to
toordownto.- Return type:
- Returns:
Formatted direction.
- classmethod __contains__(value)
Return True if value is in cls.
value is in cls if: 1) value is a member of cls, or 2) value is the value of one of the cls’s members. 3) value is a pseudo-member (flags)
- classmethod __getitem__(name)
Return the member matching name.
- classmethod __iter__()
Return members in definition order.
- classmethod __len__()
Return the number of members (no aliases)
- class pyVHDLModel.Base.Mode(*values)[source]
A
Modeis an enumeration. It represents the direction of data exchange (in,out, …) for objects in generic, port or parameter lists.In case no mode is defined,
Defaultis used, so the mode is inferred from context.Inheritance
- Default = 0
Mode not defined, thus it’s context dependent.
- In = 1
Input
- Out = 2
Output
- InOut = 3
Bi-directional
- Buffer = 4
Buffered output
- Linkage = 5
undocumented
- classmethod __contains__(value)
Return True if value is in cls.
value is in cls if: 1) value is a member of cls, or 2) value is the value of one of the cls’s members. 3) value is a pseudo-member (flags)
- classmethod __getitem__(name)
Return the member matching name.
- classmethod __iter__()
Return members in definition order.
- classmethod __len__()
Return the number of members (no aliases)
- class pyVHDLModel.Base.ModelEntity(parent=None)[source]
ModelEntityis the base-class for all classes in the VHDL language model, except for mixin classes (see multiple inheritance) and enumerations.Each entity in this model has a reference to its parent entity. Therefore, a protected variable
_parentis available and a readonly propertyParent.Inheritance
- Parameters:
parent (ModelEntity | None)
- __init__(parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity|None) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity Reference to a parent entity in the logical model hierarchy.
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent).- Returns:
Reference to the parent entity.
- class pyVHDLModel.Base.NamedEntityMixin(identifier)[source]
A
NamedEntityMixinis a mixin class for all VHDL entities that have identifiers.Protected variables
_identifierand_normalizedIdentifierare available to derived classes as well as two readonly propertiesIdentifierandNormalizedIdentifierfor public access.Inheritance
- Parameters:
identifier (str)
- __init__(identifier)[source]
Initializes a named entity.
- Parameters:
identifier (
str) – Identifier (name) of the model entity.- Return type:
None
- class pyVHDLModel.Base.MultipleNamedEntityMixin(identifiers)[source]
A
MultipleNamedEntityMixinis a mixin class for all VHDL entities that declare multiple instances at once by defining multiple identifiers.Protected variables
_identifiersand_normalizedIdentifiersare available to derived classes as well as two readonly propertiesIdentifiersandNormalizedIdentifiersfor public access.Inheritance
- class pyVHDLModel.Base.LabeledEntityMixin(label)[source]
A
LabeledEntityMixinis a mixin class for all VHDL entities that can have labels.protected variables
_labeland_normalizedLabelare available to derived classes as well as two readonly propertiesLabelandNormalizedLabelfor public access.Inheritance
- Parameters:
label (str | None)
- class pyVHDLModel.Base.DocumentedEntityMixin(documentation)[source]
A
DocumentedEntityMixinis a mixin class for all VHDL entities that can have an associated documentation.A protected variable
_documentationis available to derived classes as well as a readonly propertyDocumentationfor public access.Inheritance
- Parameters:
documentation (str | None)
- class pyVHDLModel.Base.ConditionalMixin(condition=None)[source]
A
ConditionalMixinis a mixin-class for all statements with a condition.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(condition=None)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal |
None) – The expression representing the condition.- Return type:
None
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.BranchMixin[source]
A
BranchMixinis a mixin-class for all statements with branches.Inheritance
- class pyVHDLModel.Base.ConditionalBranchMixin(condition)[source]
A
BaseBranchis a mixin-class for all branch statements with a condition.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- __init__(condition)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal) – The expression representing the condition.
- Return type:
None
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.IfBranchMixin(condition)[source]
A
BaseIfBranchis a mixin-class for all if-branches.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition).- Returns:
The expression representing the condition of a statement.
- __init__(condition)
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal) – The expression representing the condition.
- Return type:
None
- class pyVHDLModel.Base.ElsifBranchMixin(condition)[source]
A
BaseElsifBranchis a mixin-class for all elsif-branches.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition).- Returns:
The expression representing the condition of a statement.
- __init__(condition)
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal) – The expression representing the condition.
- Return type:
None
- class pyVHDLModel.Base.ElseBranchMixin[source]
A
BaseElseBranchis a mixin-class for all else-branches.Inheritance
- __init__()
- Return type:
None
- class pyVHDLModel.Base.ReportStatementMixin(message=None, severity=None)[source]
A
MixinReportStatementis a mixin-class for all report and assert statements.Inheritance
- Parameters:
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(message=None, severity=None)[source]
- Parameters:
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None
- class pyVHDLModel.Base.AssertStatementMixin(condition, message=None, severity=None)[source]
A
MixinAssertStatementis a mixin-class for all assert statements.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(condition, message=None, severity=None)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal) – The expression representing the condition.
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.BaseChoice(parent=None)[source]
A
Choiceis a base-class for all choices.Inheritance
- Parameters:
parent (ModelEntity | None)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent).- Returns:
Reference to the parent entity.
- __init__(parent=None)
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity|None) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.BaseCase(parent=None)[source]
A
Caseis a base-class for all cases.Inheritance
- Parameters:
parent (ModelEntity | None)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent).- Returns:
Reference to the parent entity.
- __init__(parent=None)
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity|None) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.Range(leftBound, rightBound, direction, parent=None)[source]
Inheritance
- Parameters:
leftBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
rightBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
direction (<property object at 0x7fef8c492c50>)
parent (ModelEntity)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent).- Returns:
Reference to the parent entity.
- __annotate_func__()
- __init__(leftBound, rightBound, direction, parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity) – The parent model entity of this entity.leftBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
rightBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
direction (<property object at 0x7fef8c492c50>)
- Return type:
None
- _parent: ModelEntity
Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.WaveformElement(expression, after=None, parent=None)[source]
Inheritance
- Parameters:
expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
after (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
parent (ModelEntity)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent).- Returns:
Reference to the parent entity.
- __annotate_func__()
- _parent: ModelEntity
Reference to a parent entity in the logical model hierarchy.
- __init__(expression, after=None, parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity) – The parent model entity of this entity.expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
after (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None