pyVHDLModel.Base¶

This module contains parts of an abstract document language model for VHDL.

Base-classes for the VHDL language model.

Variables

ExpressionUnion

Classes

Direction: An enumeration representing a direction in a range (to or downto).
Mode: A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in
ModelEntity: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
NamedEntityMixin: A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.
MultipleNamedEntityMixin: A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by
LabeledEntityMixin: A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.
DocumentedEntityMixin: A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.
ConditionalMixin: A BaseConditional is a mixin-class for all statements with a condition.
BranchMixin: A BaseBranch is a mixin-class for all statements with branches.
ConditionalBranchMixin: A BaseBranch is a mixin-class for all branch statements with a condition.
IfBranchMixin: A BaseIfBranch is a mixin-class for all if-branches.
ElsifBranchMixin: A BaseElsifBranch is a mixin-class for all elsif-branches.
ElseBranchMixin: A BaseElseBranch is a mixin-class for all else-branches.
ReportStatementMixin: A MixinReportStatement is a mixin-class for all report and assert statements.
AssertStatementMixin: A MixinAssertStatement is a mixin-class for all assert statements.
BaseChoice: A Choice is a base-class for all choices.
BaseCase: A Case is a base-class for all cases.
Range: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
WaveformElement: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

Variables

pyVHDLModel.Base.ExpressionUnion¶

typing.Union[ForwardRef('BaseExpression'), ForwardRef('QualifiedExpression'), ForwardRef('FunctionCall'), ForwardRef('TypeConversion'), ForwardRef('Literal')]

alias of Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]

Classes

class pyVHDLModel.Base.Direction[source]¶

An enumeration representing a direction in a range (to or downto).

Inheritance

To = 0¶: Ascending direction

DownTo = 1¶: Descending direction

class pyVHDLModel.Base.Mode[source]¶

A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in generic, port or parameter lists.

In case no mode is defined, Default is used, so the mode is inferred from context.

Inheritance

Default = 0¶: Mode not defined, thus it’s context dependent.

In = 1¶: Input

Out = 2¶: Output

InOut = 3¶: Bi-directional

Buffer = 4¶: Buffered output

Linkage = 5¶: undocumented

class pyVHDLModel.Base.ModelEntity[source]¶

ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple inheritance) and enumerations.

Each entity in this model has a reference to its parent entity. Therefore, a protected variable _parent is available and a readonly property Parent.

Inheritance

__init__()[source]¶: Initializes a VHDL model entity.

_parent: ModelEntity¶: Reference to a parent entity in the model.

property Parent: ModelEntity¶

Returns a reference to the parent entity.

Returns:: Parent entity.

class pyVHDLModel.Base.NamedEntityMixin[source]¶

A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.

Protected variables _identifier and _normalizedIdentifier are available to derived classes as well as two readonly properties Identifier and NormalizedIdentifier for public access.

Inheritance

__init__(identifier)[source]¶

Initializes a named entity.

Parameters:: identifier (str) – Identifier (name) of the model entity.

_identifier: str¶: The identifier of a model entity.

_normalizedIdentifier: str¶: The normalized (lower case) identifier of a model entity.

property Identifier: str¶

Returns a model entity’s identifier (name).

Returns:: Name of a model entity.

property NormalizedIdentifier: str¶

Returns a model entity’s normalized identifier (lower case name).

Returns:: Normalized name of a model entity.

class pyVHDLModel.Base.MultipleNamedEntityMixin[source]¶

A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by defining multiple identifiers.

Protected variables _identifiers and _normalizedIdentifiers are available to derived classes as well as two readonly properties Identifiers and NormalizedIdentifiers for public access.

Inheritance

__init__(identifiers)[source]¶

Initializes a multiple-named entity.

Parameters:: identifiers (Iterable[str]) – Sequence of identifiers (names) of the model entity.

_identifiers: Tuple[str]¶: A list of identifiers.

_normalizedIdentifiers: Tuple[str]¶: A list of normalized (lower case) identifiers.

property Identifiers: Tuple[str]¶

Returns a model entity’s tuple of identifiers (names).

Returns:: Tuple of identifiers.

property NormalizedIdentifiers: Tuple[str]¶

Returns a model entity’s tuple of normalized identifiers (lower case names).

Returns:: Tuple of normalized identifiers.

class pyVHDLModel.Base.LabeledEntityMixin[source]¶

A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.

protected variables _label and _normalizedLabel are available to derived classes as well as two readonly properties Label and NormalizedLabel for public access.

Inheritance

__init__(label)[source]¶

Initializes a labeled entity.

Parameters:: label (Optional[str]) – Label of the model entity.

_label: Optional[str]¶: The label of a model entity.

_normalizedLabel: Optional[str]¶: The normalized (lower case) label of a model entity.

property Label: Optional[str]¶

Returns a model entity’s label.

Returns:: Label of a model entity.

property NormalizedLabel: Optional[str]¶

Returns a model entity’s normalized (lower case) label.

Returns:: Normalized label of a model entity.

class pyVHDLModel.Base.DocumentedEntityMixin[source]¶

A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.

A protected variable _documentation is available to derived classes as well as a readonly property Documentation for public access.

Inheritance

__init__(documentation)[source]¶

Initializes a documented entity.

Parameters:: documentation (Optional[str]) – Documentation of a model entity.

_documentation: Optional[str]¶: The associated documentation of a model entity.

property Documentation: Optional[str]¶

Returns a model entity’s associated documentation.

Returns:: Associated documentation of a model entity.

class pyVHDLModel.Base.ConditionalMixin[source]¶

A BaseConditional is a mixin-class for all statements with a condition.

Inheritance

__init__(condition=None)[source]¶

Parameters:: condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.BranchMixin[source]¶

A BaseBranch is a mixin-class for all statements with branches.

Inheritance

__init__()[source]¶

class pyVHDLModel.Base.ConditionalBranchMixin[source]¶

A BaseBranch is a mixin-class for all branch statements with a condition.

Inheritance

__init__(condition)[source]¶

Parameters:: condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.IfBranchMixin[source]¶

A BaseIfBranch is a mixin-class for all if-branches.

Inheritance

__init__(condition)¶

Parameters:: condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.ElsifBranchMixin[source]¶

A BaseElsifBranch is a mixin-class for all elsif-branches.

Inheritance

__init__(condition)¶

Parameters:: condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.ElseBranchMixin[source]¶

A BaseElseBranch is a mixin-class for all else-branches.

Inheritance

__init__()¶

class pyVHDLModel.Base.ReportStatementMixin[source]¶

A MixinReportStatement is a mixin-class for all report and assert statements.

Inheritance

__init__(message=None, severity=None)[source]¶

Parameters:

message (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
severity (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.AssertStatementMixin[source]¶

A MixinAssertStatement is a mixin-class for all assert statements.

Inheritance

__init__(condition, message=None, severity=None)[source]¶

Parameters:

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
message (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
severity (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –

class pyVHDLModel.Base.BaseChoice[source]¶

A Choice is a base-class for all choices.

Inheritance

property Parent: ModelEntity¶

Returns a reference to the parent entity.

Returns:: Parent entity.

__init__()¶: Initializes a VHDL model entity.

_parent: ModelEntity¶: Reference to a parent entity in the model.

class pyVHDLModel.Base.BaseCase[source]¶

A Case is a base-class for all cases.

Inheritance

property Parent: ModelEntity¶

Returns a reference to the parent entity.

Returns:: Parent entity.

__init__()¶: Initializes a VHDL model entity.

_parent: ModelEntity¶: Reference to a parent entity in the model.

class pyVHDLModel.Base.Range[source]¶

Inheritance

property Parent: ModelEntity¶

Returns a reference to the parent entity.

Returns:: Parent entity.

__init__(leftBound, rightBound, direction)[source]¶

Initializes a VHDL model entity.

Parameters:

leftBound (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
rightBound (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
direction (Direction) –

_parent: ModelEntity¶: Reference to a parent entity in the model.

__str__()[source]¶

Return str(self).

Return type:: str

class pyVHDLModel.Base.WaveformElement[source]¶

Inheritance

property Parent: ModelEntity¶

Returns a reference to the parent entity.

Returns:: Parent entity.

_parent: ModelEntity¶: Reference to a parent entity in the model.

__init__(expression, after=None)[source]¶

Initializes a VHDL model entity.

Parameters:

expression (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –
after (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) –