pyVHDLModel.Base
This module contains parts of an abstract document language model for VHDL.
Base-classes for the VHDL language model.
Variables
Classes
Direction
: An enumeration representing a direction in a range (to
ordownto
).Mode
: AMode
is an enumeration. It represents the direction of data exchange (in
,out
, …) for objects inModelEntity
:ModelEntity
is the base-class for all classes in the VHDL language model, except for mixin classes (see multipleNamedEntityMixin
: ANamedEntityMixin
is a mixin class for all VHDL entities that have identifiers.MultipleNamedEntityMixin
: AMultipleNamedEntityMixin
is a mixin class for all VHDL entities that declare multiple instances at once byLabeledEntityMixin
: ALabeledEntityMixin
is a mixin class for all VHDL entities that can have labels.DocumentedEntityMixin
: ADocumentedEntityMixin
is a mixin class for all VHDL entities that can have an associated documentation.ConditionalMixin
: AConditionalMixin
is a mixin-class for all statements with a condition.BranchMixin
: ABranchMixin
is a mixin-class for all statements with branches.ConditionalBranchMixin
: ABaseBranch
is a mixin-class for all branch statements with a condition.IfBranchMixin
: ABaseIfBranch
is a mixin-class for all if-branches.ElsifBranchMixin
: ABaseElsifBranch
is a mixin-class for all elsif-branches.ElseBranchMixin
: ABaseElseBranch
is a mixin-class for all else-branches.ReportStatementMixin
: AMixinReportStatement
is a mixin-class for all report and assert statements.AssertStatementMixin
: AMixinAssertStatement
is a mixin-class for all assert statements.BaseChoice
: AChoice
is a base-class for all choices.BaseCase
: ACase
is a base-class for all cases.Range
:ModelEntity
is the base-class for all classes in the VHDL language model, except for mixin classes (see multipleWaveformElement
:ModelEntity
is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple
Variables
- pyVHDLModel.Base.ExpressionUnion
typing.Union[ForwardRef('BaseExpression'), ForwardRef('QualifiedExpression'), ForwardRef('FunctionCall'), ForwardRef('TypeConversion'), ForwardRef('Literal')]
alias of
BaseExpression
|QualifiedExpression
|FunctionCall
|TypeConversion
|Literal
Classes
- class pyVHDLModel.Base.Direction(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
An enumeration representing a direction in a range (
to
ordownto
).Inheritance
- To = 0
Ascending direction
- DownTo = 1
Descending direction
- class pyVHDLModel.Base.Mode(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]
A
Mode
is an enumeration. It represents the direction of data exchange (in
,out
, …) for objects in generic, port or parameter lists.In case no mode is defined,
Default
is used, so the mode is inferred from context.Inheritance
- Default = 0
Mode not defined, thus it’s context dependent.
- In = 1
Input
- Out = 2
Output
- InOut = 3
Bi-directional
- Buffer = 4
Buffered output
- Linkage = 5
undocumented
- class pyVHDLModel.Base.ModelEntity(parent=None)[source]
ModelEntity
is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple inheritance) and enumerations.Each entity in this model has a reference to its parent entity. Therefore, a protected variable
_parent
is available and a readonly propertyParent
.Inheritance
- Parameters:
parent (ModelEntity | None)
- __init__(parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
Optional
[ModelEntity
]) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity
Reference to a parent entity in the logical model hierarchy.
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent
).- Returns:
Reference to the parent entity.
- class pyVHDLModel.Base.NamedEntityMixin(identifier)[source]
A
NamedEntityMixin
is a mixin class for all VHDL entities that have identifiers.Protected variables
_identifier
and_normalizedIdentifier
are available to derived classes as well as two readonly propertiesIdentifier
andNormalizedIdentifier
for public access.Inheritance
- Parameters:
identifier (str)
- __init__(identifier)[source]
Initializes a named entity.
- Parameters:
identifier (
str
) – Identifier (name) of the model entity.- Return type:
None
- class pyVHDLModel.Base.MultipleNamedEntityMixin(identifiers)[source]
A
MultipleNamedEntityMixin
is a mixin class for all VHDL entities that declare multiple instances at once by defining multiple identifiers.Protected variables
_identifiers
and_normalizedIdentifiers
are available to derived classes as well as two readonly propertiesIdentifiers
andNormalizedIdentifiers
for public access.Inheritance
- class pyVHDLModel.Base.LabeledEntityMixin(label)[source]
A
LabeledEntityMixin
is a mixin class for all VHDL entities that can have labels.protected variables
_label
and_normalizedLabel
are available to derived classes as well as two readonly propertiesLabel
andNormalizedLabel
for public access.Inheritance
- Parameters:
label (str | None)
- class pyVHDLModel.Base.DocumentedEntityMixin(documentation)[source]
A
DocumentedEntityMixin
is a mixin class for all VHDL entities that can have an associated documentation.A protected variable
_documentation
is available to derived classes as well as a readonly propertyDocumentation
for public access.Inheritance
- Parameters:
documentation (str | None)
- class pyVHDLModel.Base.ConditionalMixin(condition=None)[source]
A
ConditionalMixin
is a mixin-class for all statements with a condition.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(condition=None)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition
).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.BranchMixin[source]
A
BranchMixin
is a mixin-class for all statements with branches.Inheritance
- class pyVHDLModel.Base.ConditionalBranchMixin(condition)[source]
A
BaseBranch
is a mixin-class for all branch statements with a condition.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- __init__(condition)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (
Union
[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.- Return type:
None
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition
).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.IfBranchMixin(condition)[source]
A
BaseIfBranch
is a mixin-class for all if-branches.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition
).- Returns:
The expression representing the condition of a statement.
- __init__(condition)
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (
Union
[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.- Return type:
None
- class pyVHDLModel.Base.ElsifBranchMixin(condition)[source]
A
BaseElsifBranch
is a mixin-class for all elsif-branches.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition
).- Returns:
The expression representing the condition of a statement.
- __init__(condition)
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (
Union
[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.- Return type:
None
- class pyVHDLModel.Base.ElseBranchMixin[source]
A
BaseElseBranch
is a mixin-class for all else-branches.Inheritance
- __init__()
- Return type:
None
- class pyVHDLModel.Base.ReportStatementMixin(message=None, severity=None)[source]
A
MixinReportStatement
is a mixin-class for all report and assert statements.Inheritance
- Parameters:
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(message=None, severity=None)[source]
- Parameters:
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None
- class pyVHDLModel.Base.AssertStatementMixin(condition, message=None, severity=None)[source]
A
MixinAssertStatement
is a mixin-class for all assert statements.Inheritance
- Parameters:
condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- __init__(condition, message=None, severity=None)[source]
Initializes a statement with a condition.
When the condition is not None, the condition’s parent reference is set to this statement.
- Parameters:
condition (
Union
[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.message (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
severity (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None
- property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal
Read-only property to access the condition of a statement (
_condition
).- Returns:
The expression representing the condition of a statement.
- class pyVHDLModel.Base.BaseChoice(parent=None)[source]
A
Choice
is a base-class for all choices.Inheritance
- Parameters:
parent (ModelEntity | None)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent
).- Returns:
Reference to the parent entity.
- __init__(parent=None)
Initializes a VHDL model entity.
- Parameters:
parent (
Optional
[ModelEntity
]) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity
Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.BaseCase(parent=None)[source]
A
Case
is a base-class for all cases.Inheritance
- Parameters:
parent (ModelEntity | None)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent
).- Returns:
Reference to the parent entity.
- __init__(parent=None)
Initializes a VHDL model entity.
- Parameters:
parent (
Optional
[ModelEntity
]) – The parent model entity of this entity.- Return type:
None
-
_parent:
ModelEntity
Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.Range(leftBound, rightBound, direction, parent=None)[source]
Inheritance
- Parameters:
leftBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
rightBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
direction (Direction)
parent (ModelEntity)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent
).- Returns:
Reference to the parent entity.
- __init__(leftBound, rightBound, direction, parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity
) – The parent model entity of this entity.leftBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
rightBound (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
direction (Direction)
- Return type:
None
- _parent: ModelEntity
Reference to a parent entity in the logical model hierarchy.
- class pyVHDLModel.Base.WaveformElement(expression, after=None, parent=None)[source]
Inheritance
- Parameters:
expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
after (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
parent (ModelEntity)
- property Parent: ModelEntity
Read-only property to access the model entity’s parent element reference in a logical hierarchy (
_parent
).- Returns:
Reference to the parent entity.
- _parent: ModelEntity
Reference to a parent entity in the logical model hierarchy.
- __init__(expression, after=None, parent=None)[source]
Initializes a VHDL model entity.
- Parameters:
parent (
ModelEntity
) – The parent model entity of this entity.expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)
after (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)
- Return type:
None