pyVHDLModel.Base

This module contains parts of an abstract document language model for VHDL.

Base-classes for the VHDL language model.

Variables

Classes

  • Direction: An enumeration representing a direction in a range (to or downto).

  • Mode: A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in

  • ModelEntity: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

  • NamedEntityMixin: A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.

  • MultipleNamedEntityMixin: A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by

  • LabeledEntityMixin: A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.

  • DocumentedEntityMixin: A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.

  • ConditionalMixin: A ConditionalMixin is a mixin-class for all statements with a condition.

  • BranchMixin: A BranchMixin is a mixin-class for all statements with branches.

  • ConditionalBranchMixin: A BaseBranch is a mixin-class for all branch statements with a condition.

  • IfBranchMixin: A BaseIfBranch is a mixin-class for all if-branches.

  • ElsifBranchMixin: A BaseElsifBranch is a mixin-class for all elsif-branches.

  • ElseBranchMixin: A BaseElseBranch is a mixin-class for all else-branches.

  • ReportStatementMixin: A MixinReportStatement is a mixin-class for all report and assert statements.

  • AssertStatementMixin: A MixinAssertStatement is a mixin-class for all assert statements.

  • BaseChoice: A Choice is a base-class for all choices.

  • BaseCase: A Case is a base-class for all cases.

  • Range: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple

  • WaveformElement: ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple


Variables

pyVHDLModel.Base.ExpressionUnion
typing.Union[ForwardRef('BaseExpression'), ForwardRef('QualifiedExpression'), ForwardRef('FunctionCall'), ForwardRef('TypeConversion'), ForwardRef('Literal')]

alias of BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal


Classes

class pyVHDLModel.Base.Direction(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

An enumeration representing a direction in a range (to or downto).

Inheritance

Inheritance diagram of Direction

To = 0

Ascending direction

DownTo = 1

Descending direction

__str__()[source]

Formats the direction to to or downto.

Return type:

str

Returns:

Formatted direction.

class pyVHDLModel.Base.Mode(value, names=<not given>, *values, module=None, qualname=None, type=None, start=1, boundary=None)[source]

A Mode is an enumeration. It represents the direction of data exchange (in, out, …) for objects in generic, port or parameter lists.

In case no mode is defined, Default is used, so the mode is inferred from context.

Inheritance

Inheritance diagram of Mode

Default = 0

Mode not defined, thus it’s context dependent.

In = 1

Input

Out = 2

Output

InOut = 3

Bi-directional

Buffer = 4

Buffered output

Linkage = 5

undocumented

__str__()[source]

Formats the direction.

Return type:

str

Returns:

Formatted direction.

class pyVHDLModel.Base.ModelEntity(parent=None)[source]

ModelEntity is the base-class for all classes in the VHDL language model, except for mixin classes (see multiple inheritance) and enumerations.

Each entity in this model has a reference to its parent entity. Therefore, a protected variable _parent is available and a readonly property Parent.

Inheritance

Inheritance diagram of ModelEntity

Parameters:

parent (ModelEntity | None)

__init__(parent=None)[source]

Initializes a VHDL model entity.

Parameters:

parent (Optional[ModelEntity]) – The parent model entity of this entity.

Return type:

None

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

class pyVHDLModel.Base.NamedEntityMixin(identifier)[source]

A NamedEntityMixin is a mixin class for all VHDL entities that have identifiers.

Protected variables _identifier and _normalizedIdentifier are available to derived classes as well as two readonly properties Identifier and NormalizedIdentifier for public access.

Inheritance

Inheritance diagram of NamedEntityMixin

Parameters:

identifier (str)

__init__(identifier)[source]

Initializes a named entity.

Parameters:

identifier (str) – Identifier (name) of the model entity.

Return type:

None

_identifier: str

The identifier of a model entity.

_normalizedIdentifier: str

The normalized (lower case) identifier of a model entity.

property Identifier: str

Returns a model entity’s identifier (name).

Returns:

Name of a model entity.

property NormalizedIdentifier: str

Returns a model entity’s normalized identifier (lower case name).

Returns:

Normalized name of a model entity.

class pyVHDLModel.Base.MultipleNamedEntityMixin(identifiers)[source]

A MultipleNamedEntityMixin is a mixin class for all VHDL entities that declare multiple instances at once by defining multiple identifiers.

Protected variables _identifiers and _normalizedIdentifiers are available to derived classes as well as two readonly properties Identifiers and NormalizedIdentifiers for public access.

Inheritance

Inheritance diagram of MultipleNamedEntityMixin

Parameters:

identifiers (Iterable[str])

__init__(identifiers)[source]

Initializes a multiple-named entity.

Parameters:

identifiers (Iterable[str]) – Sequence of identifiers (names) of the model entity.

Return type:

None

_identifiers: Tuple[str]

A list of identifiers.

_normalizedIdentifiers: Tuple[str]

A list of normalized (lower case) identifiers.

property Identifiers: Tuple[str]

Returns a model entity’s tuple of identifiers (names).

Returns:

Tuple of identifiers.

property NormalizedIdentifiers: Tuple[str]

Returns a model entity’s tuple of normalized identifiers (lower case names).

Returns:

Tuple of normalized identifiers.

class pyVHDLModel.Base.LabeledEntityMixin(label)[source]

A LabeledEntityMixin is a mixin class for all VHDL entities that can have labels.

protected variables _label and _normalizedLabel are available to derived classes as well as two readonly properties Label and NormalizedLabel for public access.

Inheritance

Inheritance diagram of LabeledEntityMixin

Parameters:

label (str | None)

__init__(label)[source]

Initializes a labeled entity.

Parameters:

label (Optional[str]) – Label of the model entity.

Return type:

None

_label: Optional[str]

The label of a model entity.

_normalizedLabel: Optional[str]

The normalized (lower case) label of a model entity.

property Label: str | None

Returns a model entity’s label.

Returns:

Label of a model entity.

property NormalizedLabel: str | None

Returns a model entity’s normalized (lower case) label.

Returns:

Normalized label of a model entity.

class pyVHDLModel.Base.DocumentedEntityMixin(documentation)[source]

A DocumentedEntityMixin is a mixin class for all VHDL entities that can have an associated documentation.

A protected variable _documentation is available to derived classes as well as a readonly property Documentation for public access.

Inheritance

Inheritance diagram of DocumentedEntityMixin

Parameters:

documentation (str | None)

__init__(documentation)[source]

Initializes a documented entity.

Parameters:

documentation (Optional[str]) – Documentation of a model entity.

Return type:

None

_documentation: Optional[str]

The associated documentation of a model entity.

property Documentation: str | None

Returns a model entity’s associated documentation.

Returns:

Associated documentation of a model entity.

class pyVHDLModel.Base.ConditionalMixin(condition=None)[source]

A ConditionalMixin is a mixin-class for all statements with a condition.

Inheritance

Inheritance diagram of ConditionalMixin

Parameters:

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal | None)

__init__(condition=None)[source]

Initializes a statement with a condition.

When the condition is not None, the condition’s parent reference is set to this statement.

Parameters:

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal, None]) – The expression representing the condition.

Return type:

None

property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

Read-only property to access the condition of a statement (_condition).

Returns:

The expression representing the condition of a statement.

class pyVHDLModel.Base.BranchMixin[source]

A BranchMixin is a mixin-class for all statements with branches.

Inheritance

Inheritance diagram of BranchMixin

__init__()[source]
Return type:

None

class pyVHDLModel.Base.ConditionalBranchMixin(condition)[source]

A BaseBranch is a mixin-class for all branch statements with a condition.

Inheritance

Inheritance diagram of ConditionalBranchMixin

Parameters:

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

__init__(condition)[source]

Initializes a statement with a condition.

When the condition is not None, the condition’s parent reference is set to this statement.

Parameters:

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

Return type:

None

property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

Read-only property to access the condition of a statement (_condition).

Returns:

The expression representing the condition of a statement.

class pyVHDLModel.Base.IfBranchMixin(condition)[source]

A BaseIfBranch is a mixin-class for all if-branches.

Inheritance

Inheritance diagram of IfBranchMixin

Parameters:

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

Read-only property to access the condition of a statement (_condition).

Returns:

The expression representing the condition of a statement.

__init__(condition)

Initializes a statement with a condition.

When the condition is not None, the condition’s parent reference is set to this statement.

Parameters:

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

Return type:

None

class pyVHDLModel.Base.ElsifBranchMixin(condition)[source]

A BaseElsifBranch is a mixin-class for all elsif-branches.

Inheritance

Inheritance diagram of ElsifBranchMixin

Parameters:

condition (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

Read-only property to access the condition of a statement (_condition).

Returns:

The expression representing the condition of a statement.

__init__(condition)

Initializes a statement with a condition.

When the condition is not None, the condition’s parent reference is set to this statement.

Parameters:

condition (Union[BaseExpression, QualifiedExpression, FunctionCall, TypeConversion, Literal]) – The expression representing the condition.

Return type:

None

class pyVHDLModel.Base.ElseBranchMixin[source]

A BaseElseBranch is a mixin-class for all else-branches.

Inheritance

Inheritance diagram of ElseBranchMixin

__init__()
Return type:

None

class pyVHDLModel.Base.ReportStatementMixin(message=None, severity=None)[source]

A MixinReportStatement is a mixin-class for all report and assert statements.

Inheritance

Inheritance diagram of ReportStatementMixin

Parameters:
__init__(message=None, severity=None)[source]
Parameters:
Return type:

None

class pyVHDLModel.Base.AssertStatementMixin(condition, message=None, severity=None)[source]

A MixinAssertStatement is a mixin-class for all assert statements.

Inheritance

Inheritance diagram of AssertStatementMixin

Parameters:
__init__(condition, message=None, severity=None)[source]

Initializes a statement with a condition.

When the condition is not None, the condition’s parent reference is set to this statement.

Parameters:
Return type:

None

property Condition: BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal

Read-only property to access the condition of a statement (_condition).

Returns:

The expression representing the condition of a statement.

class pyVHDLModel.Base.BaseChoice(parent=None)[source]

A Choice is a base-class for all choices.

Inheritance

Inheritance diagram of BaseChoice

Parameters:

parent (ModelEntity | None)

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__init__(parent=None)

Initializes a VHDL model entity.

Parameters:

parent (Optional[ModelEntity]) – The parent model entity of this entity.

Return type:

None

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Base.BaseCase(parent=None)[source]

A Case is a base-class for all cases.

Inheritance

Inheritance diagram of BaseCase

Parameters:

parent (ModelEntity | None)

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__init__(parent=None)

Initializes a VHDL model entity.

Parameters:

parent (Optional[ModelEntity]) – The parent model entity of this entity.

Return type:

None

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Base.Range(leftBound, rightBound, direction, parent=None)[source]

Inheritance

Inheritance diagram of Range

Parameters:
property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

__init__(leftBound, rightBound, direction, parent=None)[source]

Initializes a VHDL model entity.

Parameters:
Return type:

None

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

__str__()[source]

Return str(self).

Return type:

str

class pyVHDLModel.Base.WaveformElement(expression, after=None, parent=None)[source]

Inheritance

Inheritance diagram of WaveformElement

Parameters:
property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:

Reference to the parent entity.

_parent: ModelEntity

Reference to a parent entity in the logical model hierarchy.

__init__(expression, after=None, parent=None)[source]

Initializes a VHDL model entity.

Parameters:
Return type:

None