pyVHDLModel.Common

This module contains parts of an abstract document language model for VHDL.

Common definitions and Mixins are used by many classes in the model as base-classes.

Classes

Statement: A Statement is a base-class for all statements.
ProcedureCallMixin: Undocumented.
AssignmentMixin: A mixin-class for all assignment statements.
SignalAssignmentMixin: A mixin-class for all signal assignment statements.
VariableAssignmentMixin: A mixin-class for all variable assignment statements.

Classes

class pyVHDLModel.Common.Statement(label=None, parent=None)[source]

A Statement is a base-class for all statements.

Inheritance

Parameters:: label (str | None)

__init__(label=None, parent=None)[source]

Initializes a VHDL model entity.

Parameters:

parent – The parent model entity of this entity.
label (str | None)

Return type:

None

_label: Optional[str]: The label of a model entity.

_normalizedLabel: Optional[str]: The normalized (lower case) label of a model entity.

property Label: str | None

Returns a model entity’s label.

Returns:: Label of a model entity.

property NormalizedLabel: str | None

Returns a model entity’s normalized (lower case) label.

Returns:: Normalized label of a model entity.

property Parent: ModelEntity

Read-only property to access the model entity’s parent element reference in a logical hierarchy (_parent).

Returns:: Reference to the parent entity.

_parent: ModelEntity: Reference to a parent entity in the logical model hierarchy.

class pyVHDLModel.Common.ProcedureCallMixin(procedureName, parameterMappings=None)[source]

Inheritance

Parameters:

procedureName (Symbol)
parameterMappings (Iterable[ParameterAssociationItem] | None)

__init__(procedureName, parameterMappings=None)[source]

Parameters:

procedureName (Symbol)
parameterMappings (Iterable[ParameterAssociationItem] | None)

Return type:

None

class pyVHDLModel.Common.AssignmentMixin(target)[source]

A mixin-class for all assignment statements.

Inheritance

Parameters:: target (Symbol)

__init__(target)[source]

Parameters:: target (Symbol)
Return type:: None

class pyVHDLModel.Common.SignalAssignmentMixin(target)[source]

A mixin-class for all signal assignment statements.

Inheritance

Parameters:: target (Symbol)

__init__(target)

Parameters:: target (Symbol)
Return type:: None

class pyVHDLModel.Common.VariableAssignmentMixin(target, expression)[source]

A mixin-class for all variable assignment statements.

Inheritance

Parameters:

target (Symbol)
expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

__init__(target, expression)[source]

Parameters:

target (Symbol)
expression (BaseExpression | QualifiedExpression | FunctionCall | TypeConversion | Literal)

Return type:

None