Documentation Coverage Report
| Filename | Total | Covered | Missing | Coverage in % |
|---|---|---|---|---|
| 📦pyVHDLModel | 243 | 196 | 47 | 80.7% |
| 📦Formatting | 1 | 1 | 0 | 100.0% |
| ⚙️VHDL | 352 | 352 | 0 | 100.0% |
| ⚙️Association | 30 | 29 | 1 | 96.7% |
| ⚙️Base | 229 | 228 | 1 | 99.6% |
| ⚙️Common | 71 | 70 | 1 | 98.6% |
| ⚙️Concurrent | 143 | 132 | 11 | 92.3% |
| ⚙️Configuration | 42 | 41 | 1 | 97.6% |
| ⚙️Declaration | 51 | 50 | 1 | 98.0% |
| ⚙️DesignUnit | 121 | 118 | 3 | 97.5% |
| ⚙️Exception | 239 | 239 | 0 | 100.0% |
| ⚙️Expression | 369 | 361 | 8 | 97.8% |
| ⚙️IEEE | 75 | 68 | 7 | 90.7% |
| ⚙️Instantiation | 22 | 21 | 1 | 95.5% |
| ⚙️Interface | 171 | 171 | 0 | 100.0% |
| ⚙️Name | 52 | 52 | 0 | 100.0% |
| ⚙️Namespace | 31 | 26 | 5 | 83.9% |
| ⚙️Object | 43 | 43 | 0 | 100.0% |
| ⚙️PSLModel | 15 | 15 | 0 | 100.0% |
| ⚙️Predefined | 11 | 8 | 3 | 72.7% |
| ⚙️Regions | 130 | 130 | 0 | 100.0% |
| ⚙️STD | 12 | 11 | 1 | 91.7% |
| ⚙️Sequential | 143 | 143 | 0 | 100.0% |
| ⚙️Subprogram | 42 | 42 | 0 | 100.0% |
| ⚙️Symbol | 163 | 161 | 2 | 98.8% |
| ⚙️Type | 94 | 94 | 0 | 100.0% |
| ⚙️Visitor | 383 | 383 | 0 | 100.0% |
| Overall (27 files): | 3278 | 3185 | 93 | 97.2% |
| Documentation Coverage | Coverage Level |
|---|---|
| ≤10 % | almost undocumented |
| ≤20 % | almost undocumented |
| ≤30 % | almost undocumented |
| ≤40 % | poorly documented |
| ≤50 % | poorly documented |
| ≤60 % | roughly documented |
| ≤70 % | roughly documented |
| ≤80 % | roughly documented |
| ≤85 % | well documented |
| ≤90 % | well documented |
| ≤95 % | well documented |
| ≤100 % | excellent documented |
Documentation coverage analyzed with pyEDAA.Reports and visualized by pyTooling.Sphinx.