pyVHDLModel

Summary

Doc-string:

documented

File	Expected	Covered	Uncovered	Coverage
__init__.py	243	196	47	80.7%
Overall (27 files)	3278	3185	93	97.2%

Packages

Package	Expected	Covered	Uncovered	Coverage
Formatting	353	353	0	100.0%

Modules

Module	Expected	Covered	Uncovered	Coverage
Association	30	29	1	96.7%
Base	229	228	1	99.6%
Common	71	70	1	98.6%
Concurrent	143	132	11	92.3%
Configuration	42	41	1	97.6%
Declaration	51	50	1	98.0%
DesignUnit	121	118	3	97.5%
Exception	239	239	0	100.0%
Expression	369	361	8	97.8%
IEEE	75	68	7	90.7%
Instantiation	22	21	1	95.5%
Interface	171	171	0	100.0%
Name	52	52	0	100.0%
Namespace	31	26	5	83.9%
Object	43	43	0	100.0%
PSLModel	15	15	0	100.0%
Predefined	11	8	3	72.7%
Regions	130	130	0	100.0%
STD	12	11	1	91.7%
Sequential	143	143	0	100.0%
Subprogram	42	42	0	100.0%
Symbol	163	161	2	98.8%
Type	94	94	0	100.0%
Visitor	383	383	0	100.0%

Source

pyVHDLModel/__init__.pydocumentedundocumentedignoredexcludednot counted

"""
**An abstract VHDL language model.**

This package provides a unified abstract language model for VHDL. Projects reading from source files can derive own
classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
on such a model, while supporting multiple frontends.

.. admonition:: Copyright Information

   :copyright: Copyright 2017-2026 Patrick Lehmann - Bötzingen, Germany
   :copyright: Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
   :license: Apache License, Version 2.0
"""
...

__author__ =            "Patrick Lehmann"
__email__ =             "Paebbels@gmail.com"
__copyright__ =         "2016-2026, Patrick Lehmann"
__license__ =           "Apache License, Version 2.0"
__version__ =           "0.40.0rc4"
__project_url__ =       "https://github.com/VHDL/pyVHDLModel"
__documentation_url__ = "https://vhdl.github.io/pyVHDLModel"
__issue_tracker_url__ = "https://GitHub.com/VHDL/pyVHDLModel/issues"

...

ConcurrentDeclarationRegionMixin._DECLARED_ITEM_TYPES = (
	BaseType, Subprogram, Package, PackageBody, Constant, Signal, SharedVariable, File, Alias, Component, Attribute,
	AttributeSpecification, ComponentConfiguration, ModeViewDeclaration, UseClause, PSLEntity
)
Package._DECLARED_ITEM_TYPES = (*ConcurrentDeclarationRegionMixin._DECLARED_ITEM_TYPES, DeferredConstant)
SequentialDeclarationRegionMixin._DECLARED_ITEM_TYPES = (
	BaseType, Subprogram, Package, PackageBody, Constant, Variable, File, Alias, Attribute, AttributeSpecification,
	UseClause
)
ProtectedTypeDeclarationRegionMixin._DECLARED_ITEM_TYPES = (Subprogram, )

@export
@unique
class VHDLVersion(Enum):
	"""
	An enumeration for all possible version numbers for VHDL and VHDL-AMS.

	A version can be given as integer or string and is represented as a unified
	enumeration value.

	This enumeration supports compare operators.
	"""

	Any =                -1  #: Any
	VHDL87 =             87  #: VHDL-1987
	VHDL93 =             93  #: VHDL-1993
	AMS93 =            1993  #: VHDL-AMS-1993
	AMS99 =            1999  #: VHDL-AMS-1999
	VHDL2000 =         2000  #: VHDL-2000
	VHDL2002 =         2002  #: VHDL-2002
	VHDL2008 =         2008  #: VHDL-2008
	AMS2017 =          2017  #: VHDL-AMS-2017
	VHDL2019 =         2019  #: VHDL-2019
	Latest =          10000  #: Latest VHDL (2019)

	__VERSION_MAPPINGS__: dict[Union[int, str], Enum] = {
		-1:       Any,
		87:       VHDL87,
		93:       VHDL93,
		# 93:       AMS93,
		99:       AMS99,
		0:        VHDL2000,
		2:        VHDL2002,
		8:        VHDL2008,
		17:       AMS2017,
		19:       VHDL2019,
		1987:     VHDL87,
		# 1993:     VHDL93,
		1993:     AMS93,
		1999:     AMS99,
		2000:     VHDL2000,
		2002:     VHDL2002,
		2008:     VHDL2008,
		2017:     AMS2017,
		2019:     VHDL2019,
		10000:    Latest,
		"Any":    Any,
		"87":     VHDL87,
		"93":     VHDL93,
		# "93":     AMS93,
		"99":     AMS99,
		"00":     VHDL2000,
		"02":     VHDL2002,
		"08":     VHDL2008,
		"17":     AMS2017,
		"19":     VHDL2019,
		"1987":   VHDL87,
		# "1993":   VHDL93,
		"1993":   AMS93,
		"1999":   AMS99,
		"2000":   VHDL2000,
		"2002":   VHDL2002,
		"2008":   VHDL2008,
		"2017":   AMS2017,
		"2019":   VHDL2019,
		"Latest": Latest,
	}  #: Dictionary of VHDL and VHDL-AMS year codes variants as integer and strings for mapping to unique enum values.

	def __init__(self, *_) -> None:
		"""Patch the embedded MAP dictionary"""
		...

	@classmethod
	def Parse(cls, value: Union[int, str]) -> VHDLVersion:
		"""
		Parses a VHDL or VHDL-AMS year code as integer or string to an enum value.

		:param value:       VHDL/VHDL-AMS year code.
		:returns:           Enumeration value.
		:raises ValueError: If the year code is not recognized.
		"""
		...

	def __lt__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is less than the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is less than the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __le__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is less or equal than the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is less or equal than the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __gt__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is greater than the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is greater than the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __ge__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is greater or equal than the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is greater or equal than the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __ne__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is unequal to the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is unequal to the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __eq__(self, other: Any) -> bool:
		"""
		Compare two VHDL/VHDL-AMS versions if the version is equal to the second operand.

		:param other:      Parameter to compare against.
		:returns:          True if version is equal to the second operand.
		:raises TypeError: If parameter ``other`` is not of type :class:`VHDLVersion`.
		"""
		...

	def __hash__(self) -> int:
		"""
		Return the hash of the VHDL version using the underlying version number.

		.. note::

		   ``Any`` compares equal to every other member (see :meth:`__eq__`), which no hash value can satisfy
		   simultaneously for all members without collapsing every member to the same hash. This implementation
		   hashes by ``self.value``, which is internally consistent for all comparisons *except* those
		   involving ``Any`` - avoid using ``Any`` as a dict key or set member.

		:returns: Hash value of the underlying VHDL version number.
		"""
		...

	@readonly
	def IsVHDL(self) -> bool:
		"""
		Check if the version is a VHDL (not VHDL-AMS) version.

		:returns: ``True``, if the version is a VHDL version.
		"""
		...

	@readonly
	def IsAMS(self) -> bool:
		"""
		Check if the version is a VHDL-AMS (not VHDL) version.

		:returns: ``True``, if the version is a VHDL-AMS version.
		"""
		...

	def __str__(self) -> str:
		"""
		Formats the VHDL version to pattern ``VHDL'xx`` or in case of VHDL-AMS to ``VHDL-AMS'xx``.

		:returns: Formatted VHDL/VHDL-AMS version.
		"""
		...

	def __repr__(self) -> str:
		"""
		Formats the VHDL/VHDL-AMS version to pattern ``xxxx``.

		:returns: Formatted VHDL/VHDL-AMS version.
		"""
		...

@export
class IEEEFlavor(Flag):
	"""
	The ``IEEE`` VHDL library as a fixed set of predefined VHDL packages according to IEEE Std. 1076.

	Nonetheless, some vendors decided to sneak in additional packages into the ``IEEE`` namespace. |br|
	Supported flavors are:

	* ``Synopsys``
	* ``MentorGraphics``

	In addition, IEEE Std. 1076.X extensions can be loaded. |br|
	Supported extensions are:

	* ``WithVITAL`` - IEEE Std. 1076.4

	"""
	Unknown = 0         #: Unknown IEEE flavor
	IEEE = 1            #: IEEE Std. 1076 compliant list of IEEE packages.
	Synopsys = 2        #: Additional packages created by Synopsys are visible within the IEEE library.
	MentorGraphics = 4  #: Additional packages created by Mentor Graphics are visible within the IEEE library.
	WithVITAL = 32      #: Additionally load IEEE Std 1076.4 VITAL packages. (VITAL = VHDL Initiative Towards ASIC Libraries)

@export
@unique
class ObjectClass(Enum):
	"""
	An ``ObjectClass`` is an enumeration and represents an object's class (``constant``, ``signal``, ...).

	In case no *object class* is defined, ``Default`` is used, so the *object class* is inferred from context.
	"""

	Default =    0  #: Object class not defined, thus it's context dependent.
	Constant =   1  #: Constant
	Variable =   2  #: Variable
	Signal =     3  #: Signal
	File =       4  #: File
	Type =       5  #: Type
	Procedure =  6  #: Procedure
	Function =   7  #: Function

	def __str__(self) -> str:
		"""
		Formats the object class.

		:returns: Formatted object class.
		"""
		...

@export
@unique
class DesignUnitKind(Flag):
	"""
	A ``DesignUnitKind`` is an enumeration and represents the kind of design unit (``Entity``, ``Architecture``, ...).

	"""
	Context = auto()                                                             #: Context
	Package = auto()                                                             #: Package
	PackageBody = auto()                                                         #: Package Body
	Entity = auto()                                                              #: Entity
	Architecture = auto()                                                        #: Architecture
	Configuration = auto()                                                       #: Configuration

	Primary = Context | Configuration | Entity | Package                         #: List of primary design units.
	Secondary = PackageBody | Architecture                                       #: List of secondary design units.
	WithContext = Configuration | Package | Entity | PackageBody | Architecture  #: List of design units with a context.
	WithDeclaredItems = Package | Entity | PackageBody | Architecture            #: List of design units having a declaration region.

	All = Primary | Secondary                                                    #: List of all design units.

@export
@unique
class DependencyGraphVertexKind(Flag):
	"""
	A ``DependencyGraphVertexKind`` is an enumeration and represents the kind of vertex in the dependency graph.
	"""
	Document = auto()       #: A document (VHDL source file).
	Library = auto()        #: A VHDL library.

	Context = auto()        #: A context design unit.
	Package = auto()        #: A package design unit.
	PackageBody = auto()    #: A package body design unit.
	Entity = auto()         #: A entity design unit.
	Architecture = auto()   #: A architecture design unit.
	Component = auto()      #: A VHDL component.
	Configuration = auto()  #: A configuration design unit.

@export
@unique
class DependencyGraphEdgeKind(Flag):
	"""
	A ``DependencyGraphEdgeKind`` is an enumeration and represents the kind of edge in the dependency graph.
	"""
	Document =       auto()
	Library =        auto()
	Context =        auto()
	Package =        auto()
	Entity =         auto()
	Configuration =  auto()
	Component =      auto()

	DeclaredIn =     auto()
	Order =          auto()
	Reference =      auto()
	Implementation = auto()
	Instantiation =  auto()

	SourceFile =                 Document | DeclaredIn
	CompileOrder =               Document | Order

	LibraryClause =              Library | Reference
	UseClause =                  Package | Reference
	ContextReference =           Context | Reference

	EntityImplementation =       Entity | Implementation
	PackageImplementation =      Package | Implementation

	EntityInstantiation =        Entity | Instantiation
	ComponentInstantiation =     Component | Instantiation
	ConfigurationInstantiation = Configuration | Instantiation

	PackageInstantiation =       Package | Instantiation

@export
@unique
class ObjectGraphVertexKind(Flag):
	"""
	A ``ObjectGraphVertexKind`` is an enumeration and represents the kind of vertex in the object graph.
	"""
	Type =             auto()
	Subtype =          auto()

	Constant =         auto()
	DeferredConstant = auto()
	Variable =         auto()
	Signal =           auto()
	File =             auto()

	Alias =            auto()

@export
@unique
class ObjectGraphEdgeKind(Flag):
	"""
	A ``ObjectGraphEdgeKind`` is an enumeration and represents the kind of edge in the object graph.
	"""
	BaseType = auto()
	Subtype =  auto()

	ReferenceInExpression = auto()

@export
class Design(ModelEntity, AllowBlackboxMixin):
	"""
	A ``Design`` represents set of VHDL libraries as well as all loaded and analysed source files (see :class:`~pyVHDLModel.Document`).

	It's the root of this code document-object-model (CodeDOM). It contains at least one VHDL library (see :class:`~pyVHDLModel.Library`). When the design is
	analysed (see :meth:`Analyze`), multiple graph data structures will be created and populated with vertices and edges. As a first result, the design's compile
	order and hierarchy can be iterated. As a second result, the design's *top-level* is identified and referenced from the design (see :attr:`TopLevel`).

	The *design* contains references to the following graphs:

	* :attr:`DependencyGraph`
	* :attr:`CompileOrderGraph`
	* :attr:`HierarchyGraph`
	* :attr:`ObjectGraph`
	"""
	_name:              Nullable[str]         #: Name of the design.
	_libraries:         dict[str, Library]    #: List of all libraries defined for a design.
	_documents:         list[Document]        #: List of all documents loaded for a design.
	_documentsByPath:   dict[Path, Document]  #: The documents loaded for a design, indexed by path.
	_dependencyGraph:   Graph                 #: The graph of all dependencies in the designs.
	_compileOrderGraph: Graph                 #: A graph derived from dependency graph containing the order of documents for compilation.
	_hierarchyGraph:    Graph                 #: A graph derived from dependency graph containing the design hierarchy.
	_objectGraph:       Graph                 #: The graph of all types and objects in the design.
	_toplevel:          Union[Entity, Configuration]  #: When computed, the toplevel design unit is cached in this field.

	def __init__(
		self,
		name:          Nullable[str] = None,
		allowBlackbox: bool = False
	) -> None:
		"""
		Initialize a VHDL design.

		:param name:          Name of the design.
		:param allowBlackbox: Specify if blackboxes are allowed in this design.
		"""
		...

	@readonly
	def Name(self) -> Nullable[str]:
		"""
		Read-only property to access the design's name (:attr:`_name`).

		:returns: The name of the design.
		"""
		...

	@readonly
	def Libraries(self) -> dict[str, Library]:
		"""
		Read-only property to access the dictionary of library names and VHDL libraries (:attr:`_libraries`).

		:returns: A dictionary of library names and VHDL libraries.
		"""
		...

	@readonly
	def Documents(self) -> list[Document]:
		"""
		Read-only property to access the list of all documents (VHDL source files) loaded for this design (:attr:`_documents`).

		:returns: A list of all documents.
		"""
		...

	@readonly
	def CompileOrderGraph(self) -> Graph:
		"""
		Read-only property to access the compile-order graph (:attr:`_compileOrderGraph`).

		:returns: Reference to the compile-order graph.
		"""
		...

	@readonly
	def DependencyGraph(self) -> Graph:
		"""
		Read-only property to access the dependency graph (:attr:`_dependencyGraph`).

		:returns: Reference to the dependency graph.
		"""
		...

	@readonly
	def HierarchyGraph(self) -> Graph:
		"""
		Read-only property to access the hierarchy graph (:attr:`_hierarchyGraph`).

		:returns: Reference to the hierarchy graph.
		"""
		...

	@readonly
	def ObjectGraph(self) -> Graph:
		"""
		Read-only property to access the object graph (:attr:`_objectGraph`).

		:returns: Reference to the object graph.
		"""
		...

	@readonly
	def TopLevel(self) -> Union[Entity, Configuration]:
		"""
		Read-only property to access the design's *top-level* (:attr:`_toplevel`).

		When called the first time, the hierarchy graph is checked for its root elements. When there is only one root element in the graph, a new field ``toplevel``
		is added to :attr:`_hierarchyGraph` referencing that single element. In addition, the result is cached in :attr:`_toplevel`.

		:returns:                   Reference to the design's *top-level*.
		:raises VHDLModelException: If the hierarchy graph is not yet computed from dependency graph.
		:raises VHDLModelException: If there is more than one *top-level*.
		"""
		...

	def LoadStdLibrary(self) -> Library:
		"""
		Load the predefined VHDL library ``std`` into the design.

		This will create a virtual source code file ``std.vhdl`` and register VHDL design units of library ``std`` to that file.

		:returns: The library object of library ``std``.
		"""
		...

	def LoadIEEELibrary(self, flavor: Nullable[IEEEFlavor] = None) -> Library:
		"""
		Load the predefined VHDL library ``ieee`` into the design.

		This will create a virtual source code file ``ieee.vhdl`` and register VHDL design units of library ``ieee`` to that file.

		:param flavor: Select the IEEE library flavor: IEEE, Synopsys, MentorGraphics.
		:returns:      The library object of library ``ieee``.
		"""
		...

	def AddLibrary(self, library: Library) -> None:
		"""
		Add a VHDL library to the design.

		Ensure the libraries name doesn't collide with existing libraries in the design. |br|
		If ok, set the libraries parent reference to the design.

		:param library:                                Library object to loaded.
		:raises LibraryExistsInDesignError:            If the library already exists in the design.
		:raises LibraryRegisteredToForeignDesignError: If library is already used by a different design.
		"""
		...

	def RemoveLibrary(self, library: Library) -> None:
		"""
		Remove a VHDL library from the design.

		The library is detached: its parent is cleared. Its design units stay design units of the library, so the library
		can be added to a design again (:meth:`AddLibrary`).

		:param library:            The VHDL library to remove.
		:raises ValueError:        If parameter 'library' is ``None``.
		:raises TypeError:         If parameter 'library' is not of type :class:`Library`.
		:raises NotAChildError:    If parameter 'library' is not a library of this design.
		:raises LibraryInUseError: If documents of this design still use the library.

		.. seealso::

		   :meth:`AddLibrary`
		      |rarr| Add a VHDL library to the design.
		   :meth:`RemoveDocument`
		      |rarr| Remove a document from the design.
		"""
		...

	def GetLibrary(self, libraryName: str) -> Library:
		"""
		Return an (existing) VHDL library object of name ``libraryName``.

		If the requested VHDL library doesn't exist, a new VHDL library with that name will be created.

		:param libraryName: Name of the requested VHDL library.
		:returns:           The VHDL library object.
		"""
		...

	def GetEntity(self, libraryName: str, entityName: str) -> Entity:
		"""
		Return the entity named ``entityName`` from the library named ``libraryName``.

		The lookup is case-insensitive. Nothing is created, if the library or entity doesn't exist.

		:param libraryName:           Name of the library containing the entity.
		:param entityName:            Name of the requested entity.
		:returns:                     The entity.
		:raises ValueError:           If parameter 'libraryName' is None or empty.
		:raises TypeError:            If parameter 'libraryName' is not of type :class:`str`.
		:raises ValueError:           If parameter 'entityName' is None or empty.
		:raises TypeError:            If parameter 'entityName' is not of type :class:`str`.
		:raises LibraryNotFoundError: If the library doesn't exist in the design.
		:raises EntityNotFoundError:  If the entity doesn't exist in the library.
		"""
		...

	def SearchEntity(self, entityName: str) -> tuple[Entity, ...]:
		"""
		Return all entities named ``entityName`` from the libraries of the design.

		The search is case-insensitive. Each entity references its library by
		:attr:`~pyVHDLModel.DesignUnit.DesignUnit.Library`.

		:param entityName:  Name of the searched entity.
		:returns:           Tuple of entities in the order of the design's libraries, empty if no library contains one.
		:raises ValueError: If parameter 'entityName' is None or empty.
		:raises TypeError:  If parameter 'entityName' is not of type :class:`str`.
		"""
		...

	def GetPackage(self, libraryName: str, packageName: str) -> Package:
		"""
		Return the package named ``packageName`` from the library named ``libraryName``.

		The lookup is case-insensitive. Nothing is created, if the library or package doesn't exist.

		:param libraryName:           Name of the library containing the package.
		:param packageName:           Name of the requested package.
		:returns:                     The package.
		:raises ValueError:           If parameter 'libraryName' is None or empty.
		:raises TypeError:            If parameter 'libraryName' is not of type :class:`str`.
		:raises ValueError:           If parameter 'packageName' is None or empty.
		:raises TypeError:            If parameter 'packageName' is not of type :class:`str`.
		:raises LibraryNotFoundError: If the library doesn't exist in the design.
		:raises PackageNotFoundError: If the package doesn't exist in the library.
		"""
		...

	def SearchPackage(self, packageName: str) -> tuple[Package, ...]:
		"""
		Return all packages named ``packageName`` from the libraries of the design.

		The search is case-insensitive. Each package references its library by
		:attr:`~pyVHDLModel.DesignUnit.DesignUnit.Library`.

		:param packageName: Name of the searched package.
		:returns:           Tuple of packages in the order of the design's libraries, empty if no library contains one.
		:raises ValueError: If parameter 'packageName' is None or empty.
		:raises TypeError:  If parameter 'packageName' is not of type :class:`str`.
		"""
		...

	def GetConfiguration(self, libraryName: str, configurationName: str) -> Configuration:
		"""
		Return the configuration named ``configurationName`` from the library named ``libraryName``.

		The lookup is case-insensitive. Nothing is created, if the library or configuration doesn't exist.

		:param libraryName:                 Name of the library containing the configuration.
		:param configurationName:           Name of the requested configuration.
		:returns:                           The configuration.
		:raises ValueError:                 If parameter 'libraryName' is None or empty.
		:raises TypeError:                  If parameter 'libraryName' is not of type :class:`str`.
		:raises ValueError:                 If parameter 'configurationName' is None or empty.
		:raises TypeError:                  If parameter 'configurationName' is not of type :class:`str`.
		:raises LibraryNotFoundError:       If the library doesn't exist in the design.
		:raises ConfigurationNotFoundError: If the configuration doesn't exist in the library.
		"""
		...

	def SearchConfiguration(self, configurationName: str) -> tuple[Configuration, ...]:
		"""
		Return all configurations named ``configurationName`` from the libraries of the design.

		The search is case-insensitive. Each configuration references its library by
		:attr:`~pyVHDLModel.DesignUnit.DesignUnit.Library`.

		:param configurationName: Name of the searched configuration.
		:returns:                 Tuple of configurations in the order of the design's libraries, empty if no library
		                          contains one.
		:raises ValueError:       If parameter 'configurationName' is None or empty.
		:raises TypeError:        If parameter 'configurationName' is not of type :class:`str`.
		"""
		...

	def GetContext(self, libraryName: str, contextName: str) -> Context:
		"""
		Return the context named ``contextName`` from the library named ``libraryName``.

		The lookup is case-insensitive. Nothing is created, if the library or context doesn't exist.

		:param libraryName:           Name of the library containing the context.
		:param contextName:           Name of the requested context.
		:returns:                     The context.
		:raises ValueError:           If parameter 'libraryName' is None or empty.
		:raises TypeError:            If parameter 'libraryName' is not of type :class:`str`.
		:raises ValueError:           If parameter 'contextName' is None or empty.
		:raises TypeError:            If parameter 'contextName' is not of type :class:`str`.
		:raises LibraryNotFoundError: If the library doesn't exist in the design.
		:raises ContextNotFoundError: If the context doesn't exist in the library.
		"""
		...

	def SearchContext(self, contextName: str) -> tuple[Context, ...]:
		"""
		Return all contexts named ``contextName`` from the libraries of the design.

		The search is case-insensitive. Each context references its library by
		:attr:`~pyVHDLModel.DesignUnit.DesignUnit.Library`.

		:param contextName: Name of the searched context.
		:returns:           Tuple of contexts in the order of the design's libraries, empty if no library contains one.
		:raises ValueError: If parameter 'contextName' is None or empty.
		:raises TypeError:  If parameter 'contextName' is not of type :class:`str`.
		"""
		...

	def AddDocument(self, document: Document, library: Library) -> None:
		"""
		Add a document (VHDL source file) to the design and register all embedded design units to the given VHDL library.

		All checks are done, before the design, the document or the library is changed.

		.. rubric:: Algorithm

		1. Check the document isn't a document of a design, and the design contains no document of the same path.
		2. Check none of the document's entities, architectures, packages, package bodies, configurations and contexts
		   exists in the library.
		3. Add the document to the design and set the document's library.
		4. Add the document's entities, architectures, packages, package bodies, configurations and contexts to the
		   library and update their library membership.

		:param document:                           The VHDL source code file.
		:param library:                            The VHDL library used to register the embedded design units to.
		:raises ValueError:                        If parameter 'document' is ``None``.
		:raises TypeError:                         If parameter 'document' is not of type :class:`Document`.
		:raises AlreadyInDesignError:              If parameter 'document' is already a document of a design.
		:raises DuplicateDocumentError:            If the design already contains a document of the same path.
		:raises ValueError:                        If parameter 'library' is ``None``.
		:raises TypeError:                         If parameter 'library' is not of type :class:`Library`.
		:raises LibraryNotRegisteredError:         If the given VHDL library is not a library in the design.
		:raises EntityExistsInLibraryError:        If the processed entity's name is already existing in the VHDL library.
		:raises ArchitectureExistsInLibraryError:  If the processed architecture's name is already existing in the VHDL library.
		:raises PackageExistsInLibraryError:       If the processed package's name is already existing in the VHDL library.
		:raises PackageBodyExistsError:            If the processed package body's name is already existing in the VHDL library.
		:raises ConfigurationExistsInLibraryError: If the processed configuration's name is already existing in the VHDL library.
		:raises ContextExistsInLibraryError:       If the processed context's name is already existing in the VHDL library.

		.. seealso::

		   :meth:`RemoveDocument`
		      |rarr| Remove a document from the design.
		"""
		...

	def RemoveDocument(self, document: Document) -> None:
		"""
		Remove a document (VHDL source file) from the design.

		The document is detached: its parent and library are cleared. Its entities, architectures, packages, package bodies,
		configurations and contexts leave the library, and their parent is cleared. The design units stay design units of
		the document, so the document can be added to a design again.

		:param document:        The VHDL source code file.
		:raises ValueError:     If parameter 'document' is ``None``.
		:raises TypeError:      If parameter 'document' is not of type :class:`Document`.
		:raises NotAChildError: If parameter 'document' is not a document of this design.

		.. seealso::

		   :meth:`AddDocument`
		      |rarr| Add a document to the design.
		"""
		...

	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
		"""
		Iterate all design units in the design.

		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.

		.. rubric:: Algorithm

		1. Iterate all VHDL libraries.

		   1. Iterate all contexts in that library.
		   2. Iterate all packages in that library.
		   3. Iterate all package bodies in that library.
		   4. Iterate all entites in that library.
		   5. Iterate all architectures in that library.
		   6. Iterate all configurations in that library.

		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
		:returns:      A generator to iterate all matched design units in the design.

		.. seealso::

		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
		     Iterate all design units in the library.
		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
		     Iterate all design units in the document.
		"""
		...

	def Analyze(self) -> None:
		"""
		Analyze the whole design.

		The analysis can be repeated, e.g. after the design was changed: the previous analysis is reset first.

		.. rubric:: Algorithm

		1. Reset a previous analysis. |br|
		   |rarr| :meth:`ResetAnalysis`
		2. Analyze dependencies of design units. |br|
		   This will also yield the design hierarchy and the compiler order.
		3. Analyze dependencies of types and objects.

		.. seealso::

		   :meth:`ResetAnalysis`
		     Reset everything an analysis derived.

		   :meth:`AnalyzeDependencies`
		     Analyze the dependencies of design units.

		   :meth:`AnalyzeObjects`
		     Analyze the dependencies of types and objects.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def ResetAnalysis(self) -> None:
		"""
		Reset everything an analysis (:meth:`Analyze`) derived, so the design can be analyzed again.

		Everything built by the user is kept: libraries, documents, design units, declarations and the declarations in
		namespaces. Lookup tables built by indexing (e.g. :meth:`IndexPackages`) are kept too, as indexing again yields
		the same lookup tables. Resetting a design, which wasn't analyzed, changes nothing.

		.. rubric:: Algorithm

		1. Delete the dependency, compile-order, hierarchy and object graph (:meth:`~pyTooling.Graph.Graph.Delete`), so
		   their vertices and edges are freed at once, replace them by empty graphs, and forget the top-level.
		2. Clear the references to vertices of all libraries, documents and design units.
		3. Clear the references of all design units: referenced libraries, packages and contexts, the symbols of library
		   clauses, use clauses and context references, and the items imported into namespaces.
		4. Unlink architectures from entities and package bodies from packages: an entity's architectures, a package's
		   body, the symbols referencing the entity or package, and the link to the parent namespace.
		5. Unlink package instantiations from their generic package: the symbol and the components copied from it.
		6. Unbind all components: their entity and blackbox state.
		7. Clear the symbols of entity and component instantiations.
		"""
		...

	def AnalyzeDependencies(self) -> None:
		"""
		Analyze the dependencies of design units.

		.. rubric:: Algorithm

		1. Create all vertices of the dependency graph by iterating all design units in all libraries. |br|
		   |rarr| :meth:`CreateDependencyGraph`
		2. Create the compile order graph. |br|
		   |rarr| :meth:`CreateCompileOrderGraph`
		3. Index all packages. |br|
		   |rarr| :meth:`IndexPackages`
		4. Index all entities. |br|
		   |rarr| :meth:`IndexEntities`
		5. Index all architectures. |br|
		   |rarr| :meth:`IndexArchitectures`
		6. Link all contexts |br|
		   |rarr| :meth:`LinkContexts`
		7. Link all architectures. |br|
		   |rarr| :meth:`LinkArchitectures`
		8. Link all package bodies. |br|
		   |rarr| :meth:`LinkPackageBodies`
		9. Link all package instances. |br|
		   |rarr| :meth:`LinkPackageInstances`
		10. Link all library references. |br|
		    |rarr| :meth:`LinkLibraryReferences`
		11. Link all package references. |br|
		    |rarr| :meth:`LinkPackageReferences`
		12. Link all context references. |br|
		    |rarr| :meth:`LinkContextReferences`
		13. Link all components. |br|
		    |rarr| :meth:`LinkComponents`
		14. Link all instantiations. |br|
		    |rarr| :meth:`LinkInstantiations`
		15. Create the hierarchy graph. |br|
		    |rarr| :meth:`CreateHierarchyGraph`
		16. Compute the compile order. |br|
		    |rarr| :meth:`ComputeCompileOrder`

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def AnalyzeObjects(self) -> None:
		"""
		Analyze the dependencies of types and objects.

		.. rubric:: Algorithm

		1. Index all entities. |br|
		   |rarr| :meth:`IndexEntities`
		2. Index all package bodies. |br|
		   |rarr| :meth:`IndexPackageBodies`
		3. Import objects. |br|
		   |rarr| :meth:`ImportObjects`
		4. Create the type and object graph. |br|
		   |rarr| :meth:`CreateTypeAndObjectGraph`

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def CreateDependencyGraph(self) -> None:
		"""
		Create all vertices of the dependency graph by iterating all design units in all libraries.

		This method will purely create a sea of vertices without any linking between vertices. The edges will be created later by other methods. |br|
		See :meth:`AnalyzeDependencies` for these methods and their algorithmic order.

		Each vertex has the following properties:

		* The vertex' ID is the design unit's identifier.
		* The vertex' value references the design unit.
		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
		* A key-value-pair called ``predefined`` denotes if the referenced design unit is a predefined language entity.

		.. rubric:: Algorithm

		1. Iterate all libraries in the design.

		   * Create a vertex for that library and reference the library by the vertex' value field. |br|
		     In return, set the library's :attr:`~pyVHDLModel.Library._dependencyVertex` field to reference the created vertex.

		   1. Iterate all contexts in that library.

		      * Create a vertex for that context and reference the context by the vertex' value field. |br|
		        In return, set the context's :attr:`~pyVHDLModel.DesignUnit.Context._dependencyVertex` field to reference the created vertex.

		   2. Iterate all packages in that library.

		      * Create a vertex for that package and reference the package by the vertex' value field. |br|
		        In return, set the package's :attr:`~pyVHDLModel.DesignUnit.Package._dependencyVertex` field to reference the created vertex.

		   3. Iterate all package bodies in that library.

		      * Create a vertex for that package body and reference the package body by the vertex' value field. |br|
		        In return, set the package body's :attr:`~pyVHDLModel.DesignUnit.PackageBody._dependencyVertex` field to reference the created vertex.

		   4. Iterate all entities in that library.

		      * Create a vertex for that entity and reference the entity by the vertex' value field. |br|
		        In return, set the entity's :attr:`~pyVHDLModel.DesignUnit.Entity._dependencyVertex` field to reference the created vertex.

		   5. Iterate all architectures in that library.

		      * Create a vertex for that architecture and reference the architecture by the vertex' value field. |br|
		        In return, set the architecture's :attr:`~pyVHDLModel.DesignUnit.Architecture._dependencyVertex` field to reference the created vertex.

		   6. Iterate all configurations in that library.

		      * Create a vertex for that configuration and reference the configuration by the vertex' value field. |br|
		        In return, set the configuration's :attr:`~pyVHDLModel.DesignUnit.Configuration._dependencyVertex` field to reference the created vertex.
		"""
		...

	def CreateCompileOrderGraph(self) -> None:
		"""
		Create a compile-order graph with bidirectional references to the dependency graph.

		Add vertices representing a document (VHDL source file) to the dependency graph. Each "document" vertex in dependency graph is copied into the compile-order
		graph and bidirectionally referenced.

		In addition, each vertex of a corresponding design unit in a document is linked to the vertex representing that document to express the design unit in
		document relationship.

		Each added vertex has the following properties:

		* The vertex' ID is the document's filename.
		* The vertex' value references the document.
		* A key-value-pair called ``kind`` denotes the vertex's kind as an enumeration value of type :class:`DependencyGraphVertexKind`.
		* A key-value-pair called ``predefined`` does not exist.

		.. rubric:: Algorithm

		1. Iterate all documents in the design.

		   * Create a vertex for that document with the document's path as vertex ID and reference the document by the
		     vertex' value field. |br|
		     In return, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the created vertex.
		   * Copy the vertex from dependency graph to compile-order graph and link both vertices bidirectionally. |br|
		     In addition, set the documents's :attr:`~pyVHDLModel.Document._dependencyVertex` field to reference the copied vertex.

		     * Add a key-value-pair called ``compileOrderVertex`` to the dependency graph's vertex.
		     * Add a key-value-pair called ``dependencyVertex`` to the compiler-order graph's vertex.

		   1. Iterate the documents design units and create an edge from the design unit's corresponding dependency vertex to the documents corresponding
		      dependency vertex. This expresses a "design unit is located in document" relation.

		      * Add a key-value-pair called `kind`` denoting the edge's kind as an enumeration value of type :class:`DependencyGraphEdgeKind`.
		"""
		...

	def ImportObjects(self) -> None:
		def _ImportObjects(package: Package) -> None:
			...

		...

	def CreateTypeAndObjectGraph(self) -> None:
		def _HandlePackage(package) -> None:
			...

		def _LinkSymbolsInExpression(expression, namespace: Namespace, typeVertex: Vertex) -> None:
			...

		def _LinkItems(package: Package) -> None:
			...

		...

	def LinkContexts(self) -> None:
		"""
		Resolves and links all items (library clauses, use clauses and nested context references) in contexts.

		It iterates all contexts in the design. Therefore, the library of the context is used as the working library. By
		default, the working library is implicitly referenced in :data:`_referencedLibraries`. In addition, a new empty
		dictionary is created in :data:`_referencedPackages` and :data:`_referencedContexts` for that working library.

		At first, all library clauses are resolved (a library clause my have multiple library reference symbols). For each
		referenced library an entry in :data:`_referencedLibraries` is generated and new empty dictionaries in
		:data:`_referencedPackages` and :data:`_referencedContexts` for that working library. In addition, a vertex in the
		dependency graph is added for that relationship.

		At second, all use clauses are resolved (a use clause my have multiple package member reference symbols). For each
		referenced package,
		"""
		...

	def LinkArchitectures(self) -> None:
		"""
		Link all architectures to corresponding entities in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all architecture groups (grouped per entity symbol's name).
		      |rarr| :meth:`pyVHDLModel.Library.LinkArchitectures`

		      * Check if entity symbol's name exists as an entity in this library.

		      1. For each architecture in the same architecture group:

		         * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
		         * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
		         * Set parent namespace of architecture's namespace to the entitie's namespace.
		         * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.

		.. seealso::

		   :meth:`LinkPackageBodies`
		     Link all package bodies to corresponding packages in all libraries.
		   :meth:`LinkPackageInstances`
		     Link all package instances to corresponding generic packages in all libraries.
		"""
		...

	def LinkPackageBodies(self) -> None:
		"""
		Link all package bodies to corresponding packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all package bodies.
		      |rarr| :meth:`pyVHDLModel.Library.LinkPackageBodies`

		      * Check if package body symbol's name exists as a package in this library.
		      * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
		      * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
		      * Set parent namespace of package body's namespace to the package's namespace.
		      * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.

		.. seealso::

		   :meth:`LinkArchitectures`
		     Link all architectures to corresponding entities in all libraries.
		   :meth:`LinkPackageInstances`
		     Link all package instances to corresponding generic packages in all libraries.
		"""
		...

	def LinkPackageInstances(self) -> None:
		"""
		Link all package instances to corresponding generic packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all package instances.
		      |rarr| :meth:`pyVHDLModel.Library.LinkPackageInstances`

          .. todo::

		         * Check if package instance's symbol's name exists as a generic package in this library.
		         * Add generic package to package instance :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
		         * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
		         * Set parent namespace of package body's namespace to the package's namespace.
		         * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.

		.. seealso::

		   :meth:`LinkArchitectures`
		     Link all architectures to corresponding entities in all libraries.
		   :meth:`LinkPackageBodies`
		     Link all package bodies to corresponding packages in all libraries.
		"""
		...

	def LinkLibraryReferences(self) -> None:
		"""
		Link all library references (library clause) to the matching VHDL library.

		.. rubric:: Algorithm

		1. Iterate all design units with contexts:

		   * If the design unit is a primary unit:

		     1. Iterate all library identifiers in ``DEFAULT_LIBRARIES`` (``std``):

		        * Get the referenced library by name from the design.
		        * Add an entry in the design unit's ``_referencedLibraries`` dictionary referencing the referenced library.
		        * Add an empty dictionary in the design unit's ``_referencedPackages`` dictionary.
		        * Add an empty dictionary in the design unit's ``_referencedContexts`` dictionary.
		        * Add an edge in the dependency graph from design unit to the referenced library.

		     2. Get the design unit's library:

		        * Add an entry in the design unit's ``_referencedLibraries`` dictionary referencing the referenced library.
		        * Add an empty dictionary in the design unit's ``_referencedPackages`` dictionary.
		        * Add an empty dictionary in the design unit's ``_referencedContexts`` dictionary.
		        * Add an edge in the dependency graph from design unit to the referenced library.

		   * If the design unit is a secondary unit:

		     * If design unit is an architecture, get the corresponding entity's referenced libraries.
		     * If design unit is a package body, get the corresponding package's referenced libraries.
		     * Otherwise, raise an exception

		     For every referenced library create new dictionary entries in the design unit's ``_referencedLibraries``.

		2. Iterate every library reference (library clause) in the design unit:

		   * Iterate every library symbol within the library reference:

		     * Get the library identifier from the symbol.
		     * Continue the inner loop, if identifier is ``work``.
		     * Get the referenced library from the design or raise an exception.
		     * Update the library symbol's target with the referenced library.
		     * Add an entry in the design unit's ``_referencedLibraries`` dictionary referencing the referenced library.
		     * Add an empty dictionary in the design unit's ``_referencedPackages`` dictionary.
		     * Add an empty dictionary in the design unit's ``_referencedContexts`` dictionary.
		     * Add an edge in the dependency graph from design unit to the referenced library.

		.. seealso::

		   :meth:`LinkPackageReferences`
		     Link *use clause*.
		   :meth:`LinkContextReferences`
		     Link *context clause*.
		   :meth:`AnalyzeDependencies`
		     Analyze dependencies and link relations.
		"""
		...

	def LinkPackageReferences(self) -> None:
		"""
		Link all package references (use clause) to the matching packages.

		.. rubric:: Algorithm

		1. Iterate all design units with contexts:

		   * If the design unit is a primary unit:

		     * If primary unit isn't package ``std.standard``:

		       1. Iterate all library, packages tuples in ``DEFAULT_PACKAGES`` (``std``: [``standard``]):

		          * Raise an exception, if library isn't listed in design unit's ``_referencedLibraries``.
		          * For every package in packages:

		            * Get the referenced package by library name and package name from the design.
		            * Add an entry in the design unit's ``_referencedPackages`` dictionary referencing the referenced package.
		            * Add an edge in the dependency graph from design unit to the referenced package.

		   * If the design unit is a secondary unit:

		     * If design unit is an architecture, get the corresponding entity's referenced packages.
		     * If design unit is a package body, get the corresponding package's referenced packages.
		     * Otherwise, raise an exception

		     For every referenced package create new dictionary entries in the design unit's ``_referencedPackages``.

		2. Iterate every package reference (use clause) in the design unit:

		   * Iterate every package symbol within the package reference:

		     1. Get the library identifier from the symbol.
		     2. Get the package identifier from the symbol.
		     3. Resolve library:

		        * If library name is ``work``, get library from design unit.
		        * If library name is not in design unit's ``_referencedLibraries``, raise an exception.
		        * Otherwise, lookup library by name in design.

		     4. Resolve package:

		        * Lookup package by name in library.

		     5. Update design unit:

		        * Update the package symbol's target with the referenced package.
		        * Add an entry in the design unit's ``_referencedPackages`` dictionary referencing the referenced package.
		        * Add an edge in the dependency graph from design unit to the referenced package.

		     6. Import public package members.

		        * If package symbol is a ``AllPackageMembersReferenceSymbol``:

		          * Iterate all components within the referenced package and import each component into the design unit's
		            namespace.

		          .. todo:: Other elements are not implemented.

		        * If package symbol is a ``PackageMemberReferenceSymbol``

		          .. todo:: Not implemented.

		        * Otherwise, raise an exception.

		.. seealso::

		   :meth:`LinkLibraryReferences`
		     Link *library clause*.
		   :meth:`LinkContextReferences`
		     Link *context clause*.
		   :meth:`AnalyzeDependencies`
		     Analyze dependencies and link relations.
		"""
		...

	def LinkContextReferences(self) -> None:
		"""
		Link all context references (context clause) to the matching context.

		.. rubric:: Algorithm

		1. Iterate all design units:

		   * Iterate all context references in the design unit:

		     * Iterate each context symbol within the context reference.

		       1. Get the library identifier from the symbol.
		       2. Get the context identifier from the symbol.
		       3. Resolve library:

		          * If library name is ``work``, get library from design unit.
		          * If library name is not in design unit's ``_referencedLibraries``, raise an exception.
		          * Otherwise, lookup library by name in design.

		       4. Resolve context:

		          * Lookup context by name in library.

		       5. Update design unit:

		          * Update the context symbol's target with the referenced context.
		          * Add an entry in the design unit's ``_referencedContexts`` dictionary referencing the referenced context.
		          * Add an edge in the dependency graph from design unit to the referenced context.

		2. Iterate all context vertices in the dependency graph (``_dependencyGraph``) in topological order:

		   * Get the context from the context vertex.
		   * Iterate all predecessor vertices (design unit vertices) of the context vertex:

		     1. Get the design unit from design unit vertex.
		     2. Iterate referenced libraries of the context:

		        * Add an entry in the design unit's ``_referencedLibraries`` dictionary referencing the referenced library.
		        * Add an empty dictionary in the design unit's ``_referencedPackages`` dictionary.

		     3. Iterate referenced packages of the context:

		        * Raise an exception if package name is already listed in ``_referencedPackages``.
		        * Add an entry in the design unit's ``_referencedPackages`` dictionary referencing the referenced package.

		.. seealso::

		   :meth:`LinkLibraryReferences`
		     Link *library clause*.
		   :meth:`LinkPackageReferences`
		     Link *use clause*.
		   :meth:`AnalyzeDependencies`
		     Analyze dependencies and link relations.
		"""
		...

	def LinkComponents(self) -> None:
		"""
		Link components to matching entities found in same VHDL library.

		.. rubric:: Algorithm

		1. Iterate all design units with component declarations (packages and architectures):

		   1. Iterate all component declarations in a package or architecture:

		      * Check if an entity with matching name can be found in the VHDL library the package is declared within. If
		        found, set the component's entity reference to that entity, otherwise check if blackboxes are allowed for
		        that component. If so, mark the component as a blackbox, otherwise, raise an exception.

		   2. Iterate concurrent statements with declaration regions (block statements, generate statements) if the design
		      unit is an architecture:

		      * If the statement is an :class:`IfGenerateStatement`:

		        1. Iterate declared components in the :class:`IfGenerateBranch`.
		        2. Iterate declared components in each :class:`ElIfGenerateBranch`.
		        3. Iterate declared components in the :class:`ElseGenerateBranch` if it exists.

		      * If the statement is an :class:`ForGenerateStatement`:

		        1. Iterate declared components.

		      * If the statement is an :class:`CaseGenerateStatement`:

		        1. Iterate declared components.
		        2. Iterate

		:raises VHDLModelException: If no entity is found for a component, which doesn't allow blackboxes.

		.. seealso::

		   :meth:`LinkInstantiations`
		     Link instantiations to components and entities.
		   :meth:`AnalyzeDependencies`
		     Analyze dependencies in a design (calls this method).
		"""
		...

	def _IterateComponents(self) -> Generator[tuple[Library, Component], None, None]:
		"""
		Iterate all components of packages and architectures, including the components declared in blocks and generate
		statements nested in architectures.

		:returns: A generator to iterate tuples of the library of the design unit and a component.
		"""
		def iterateStatements(concurrent: ConcurrentStatementsMixin) -> Generator[Component, None, None]:
			"""
			Nested function for recursion.

			:param concurrent: The language construct containing concurrent statements.
			:returns:          A generator to iterate the components declared in the nested statements.
			"""
			...

		def iterateDeclaredItems(declarationRegion: ConcurrentDeclarationRegionMixin) -> Generator[Component, None, None]:
			"""
			Nested function iterating the components declared in a declaration region.

			:param declarationRegion: The declaration region.
			:returns:                 A generator to iterate the declared components.
			"""
			...

		...

	def LinkInstantiations(self) -> None:
		...

	def IndexPackages(self) -> None:
		"""
		Index all declared items in all packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all packages |br|
		      |rarr| :meth:`pyVHDLModel.Library.IndexPackages`

		      * Index all declared items in that package. |br|
		        |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackageBodies`
		     Index all declared items in all package bodies in all libraries.
		   :meth:`IndexEntities`
		     Index all declared items in all entities in all libraries.
		   :meth:`IndexArchitectures`
		     Index all declared items in all architectures in all libraries.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexPackageBodies(self) -> None:
		"""
		Index all declared items in all packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all packages |br|
		      |rarr| :meth:`pyVHDLModel.Library.IndexPackageBodies`

		      * Index all declared items in that package body. |br|
		        |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in all packages in all libraries.
		   :meth:`IndexEntities`
		     Index all declared items in all entities in all libraries.
		   :meth:`IndexArchitectures`
		     Index all declared items in all architectures in all libraries.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexEntities(self) -> None:
		"""
		Index all declared items in all packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all packages |br|
		      |rarr| :meth:`pyVHDLModel.Library.IndexEntities`

		      * Index all declared items in that entity. |br|
		        |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in all packages in all libraries.
		   :meth:`IndexPackageBodies`
		     Index all declared items in all package bodies in all libraries.
		   :meth:`IndexArchitectures`
		     Index all declared items in all architectures in all libraries.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexArchitectures(self) -> None:
		"""
		Index all declared items in all packages in all libraries.

		.. rubric:: Algorithm

		1. Iterate all libraries:

		   1. Iterate all packages |br|
		      |rarr| :meth:`pyVHDLModel.Library.IndexArchitectures`

		      * Index all declared items in that architecture. |br|
		        |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in all packages in all libraries.
		   :meth:`IndexPackageBodies`
		     Index all declared items in all package bodies in all libraries.
		   :meth:`IndexEntities`
		     Index all declared items in all entities in all libraries.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def CreateHierarchyGraph(self) -> None:
		"""
		Create the hierarchy graph from dependency graph.

		.. rubric:: Algorithm

		1. Iterate all vertices corresponding to entities and architectures in the dependency graph:

		   * Copy these vertices to the hierarchy graph and create a bidirectional linking. |br|
		     In addition, set the referenced design unit's :attr:`~pyVHDLModel.Document._hierarchyVertex` field to reference the copied vertex.

		     * Add a key-value-pair called ``hierarchyVertex`` to the dependency graph's vertex.
		     * Add a key-value-pair called ``dependencyVertex`` to the hierarchy graph's vertex.

		2. Iterate all architectures ...

		   .. todo:: Design::CreateHierarchyGraph describe algorithm

		   1. Iterate all outbound edges

		      .. todo:: Design::CreateHierarchyGraph describe algorithm
		"""
		...

	def ComputeCompileOrder(self) -> None:
		def predicate(edge: Edge) -> bool:
			...

		...

	def IterateDocumentsInCompileOrder(self) -> Generator[Document, None, None]:
		"""
		Iterate all document in compile-order.

		.. rubric:: Algorithm

		* Check if compile-order graph was populated with vertices and its vertices are linked by edges.

		1. Iterate compile-order graph in topological order. |br|
		   :meth:`pyTooling.Graph.Graph.IterateTopologically`

		   * yield the compiler-order vertex' referenced document.

		:returns:                   A generator to iterate all documents in compile-order in the design.
		:raises VHDLModelException: If compile-order was not computed.

		.. seealso::

		   .. todo:: missing text

		      :meth:`pyVHDLModel.Design.ComputeCompileOrder`

		"""
		...

	def GetUnusedDesignUnits(self) -> list[DesignUnit]:
		...

	def __repr__(self) -> str:
		"""
		Formats a representation of the design.

		**Format:** ``Document: 'my_design'``

		:returns: String representation of the design.
		"""
		...

	__str__ = __repr__

@export
class Library(ModelEntity, NamedEntityMixin, DocumentedEntityMixin, AllowBlackboxMixin):
	"""
	A ``Library`` represents a VHDL library. It contains all *primary* and *secondary* design units.

	.. seealso::

	   * :class:`Predefined library <pyVHDLModel.Predefined.PredefinedLibrary>`
	"""

	_contexts:       dict[str, Context]                  #: Dictionary of all contexts defined in a library.
	_configurations: dict[str, Configuration]            #: Dictionary of all configurations defined in a library.
	_entities:       dict[str, Entity]                   #: Dictionary of all entities defined in a library.
	_architectures:  dict[str, dict[str, Architecture]]  #: Dictionary of all architectures defined in a library.
	_packages:       dict[str, Package]                  #: Dictionary of all packages defined in a library.
	_packageBodies:  dict[str, PackageBody]              #: Dictionary of all package bodies defined in a library.

	_dependencyVertex: Vertex  #: Reference to the vertex in the dependency graph representing the library. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateDependencyGraph`.

	def __init__(
		self,
		identifier:    str,
		documentation: Nullable[str] = None,
		allowBlackbox: Nullable[bool] = None,
		parent:        Nullable[ModelEntity] = None
	) -> None:
		"""
		Initialize a VHDL library.

		:param identifier:    Name of the VHDL library.
		:param documentation: Documentation of this VHDL library, if the caller has one to supply.
		:param allowBlackbox: Specify if blackboxes are allowed in this design.
		:param parent:        The parent model entity (design) of this VHDL library.
		"""
		...

	@property
	def Documentation(self) -> Nullable[str]:
		"""
		Property to access the library's documentation (:attr:`_documentation`).

		.. hint::

		   Unlike every other documented entity, a library's documentation cannot come from VHDL source:
		   the language has no library declaration to attach a comment to. It is therefore settable, so a
		   caller can supply one from elsewhere - a compile-order file, a project description, ...

		:returns: Associated documentation of this VHDL library.
		"""
		...

	@Documentation.setter
	def Documentation(self, documentation: Nullable[str]) -> None:
		...

	@readonly
	def Contexts(self) -> dict[str, Context]:
		"""
		Read-only property to access the dictionary of all context declarations in this library (:attr:`_contexts`).

		:returns: Dictionary of all contexts, indexed by normalized identifier.
		"""
		...

	@readonly
	def Configurations(self) -> dict[str, Configuration]:
		"""
		Read-only property to access the dictionary of all configuration declarations in this library (:attr:`_configurations`).

		:returns: Dictionary of all configurations, indexed by normalized identifier.
		"""
		...

	@readonly
	def Entities(self) -> dict[str, Entity]:
		"""
		Read-only property to access the dictionary of all entity declarations in this library (:attr:`_entities`).

		:returns: Dictionary of all entities, indexed by normalized identifier.
		"""
		...

	@readonly
	def Architectures(self) -> dict[str, dict[str, Architecture]]:
		"""
		Read-only property to access the dictionary of all architecture declarations in this library (:attr:`_architectures`).

		:returns: Dictionary of all architectures, indexed by normalized entity identifier, then by normalized
		          architecture identifier.
		"""
		...

	@readonly
	def Packages(self) -> dict[str, Package]:
		"""
		Read-only property to access the dictionary of all package declarations in this library (:attr:`_packages`).

		:returns: Dictionary of all packages, indexed by normalized identifier.
		"""
		...

	@readonly
	def PackageBodies(self) -> dict[str, PackageBody]:
		"""
		Read-only property to access the dictionary of all package body declarations in this library (:attr:`_packageBodies`).

		:returns: Dictionary of all package bodies, indexed by normalized identifier.
		"""
		...

	@readonly
	def DependencyVertex(self) -> Vertex:
		"""
		Read-only property to access the corresponding dependency vertex (:attr:`_dependencyVertex`).

		The dependency vertex references this library by its value field.

		:returns: The corresponding dependency vertex.
		"""
		...

	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
		"""
		Iterate all design units in the library.

		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.

		.. rubric:: Algorithm

		1. Iterate all contexts in that library.
		2. Iterate all packages in that library.
		3. Iterate all package bodies in that library.
		4. Iterate all entities in that library.
		5. Iterate all architectures in that library.
		6. Iterate all configurations in that library.

		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
		:returns:      A generator to iterate all matched design units in the library.

		.. seealso::

		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
		     Iterate all design units in the design.
		   :meth:`pyVHDLModel.Document.IterateDesignUnits`
		     Iterate all design units in the document.
		"""
		...

	def LinkArchitectures(self) -> None:
		"""
		Link all architectures to corresponding entities.

		.. rubric:: Algorithm

		1. Iterate all architecture groups (grouped per entity symbol's name).

		   * Check if entity symbol's name exists as an entity in this library.

		   1. For each architecture in the same architecture group:

		      * Add architecture to entities architecture dictionary :attr:`pyVHDLModel.DesignUnit.Entity._architectures`.
		      * Assign found entity to architecture's entity symbol :attr:`pyVHDLModel.DesignUnit.Architecture._entity`
		      * Set parent namespace of architecture's namespace to the entitie's namespace.
		      * Add an edge in the dependency graph from the architecture's corresponding dependency vertex to the entity's corresponding dependency vertex.

		:raises VHDLModelException: If entity name doesn't exist.
		:raises VHDLModelException: If architecture name already exists for entity.

		.. seealso::

		   :meth:`LinkPackageBodies`
		     Link all package bodies to corresponding packages.
		   :meth:`LinkPackageInstances`
		     Link all package instances to corresponding generic packages.
		"""
		...

	def LinkPackageBodies(self) -> None:
		"""
		Link all package bodies to corresponding packages.

		.. rubric:: Algorithm

		1. Iterate all package bodies.

		   * Check if package body symbol's name exists as a package in this library.
		   * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
		   * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
		   * Set parent namespace of package body's namespace to the package's namespace.
		   * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.

		:raises VHDLModelException: If package name doesn't exist.

		.. seealso::

		   :meth:`LinkArchitectures`
		     Link all architectures to corresponding entities.
		   :meth:`LinkPackageInstances`
		     Link all package instances to corresponding generic packages.
		"""
		...

	def LinkPackageInstances(self) -> None:
		"""
		Link all package instances to corresponding generic packages.

		.. rubric:: Algorithm

		1. Iterate all package instances.

		   .. todo::

		      * Check if package body symbol's name exists as a package in this library.
		      * Add package body to package :attr:`pyVHDLModel.DesignUnit.Package._packageBody`.
		      * Assign found package to package body's package symbol :attr:`pyVHDLModel.DesignUnit.PackageBody._package`
		      * Set parent namespace of package body's namespace to the package's namespace.
		      * Add an edge in the dependency graph from the package body's corresponding dependency vertex to the package's corresponding dependency vertex.

		:raises VHDLModelException: If generic package name doesn't exist.

		.. seealso::

		   :meth:`LinkArchitectures`
		     Link all architectures to corresponding entities.
		   :meth:`LinkPackageBodies`
		     Link all package bodies to corresponding packages.
		"""
		...

	def IndexPackages(self) -> None:
		"""
		Index declared items in all packages.

		.. rubric:: Algorithm

		1. Iterate all packages:

		   * Index all declared items. |br|
		     |rarr| :meth:`pyVHDLModel.DesignUnit.Package.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackageBodies`
		     Index all declared items in a package body.
		   :meth:`IndexEntities`
		     Index all declared items in an entity.
		   :meth:`IndexArchitectures`
		     Index all declared items in an architecture.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexPackageBodies(self) -> None:
		"""
		Index declared items in all package bodies.

		.. rubric:: Algorithm

		1. Iterate all package bodies:

		   * Index all declared items. |br|
		     |rarr| :meth:`pyVHDLModel.DesignUnit.PackageBody.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in a package.
		   :meth:`IndexEntities`
		     Index all declared items in an entity.
		   :meth:`IndexArchitectures`
		     Index all declared items in an architecture.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexEntities(self) -> None:
		"""
		Index declared items in all entities.

		.. rubric:: Algorithm

		1. Iterate all entities:

		   * Index all declared items. |br|
		     |rarr| :meth:`pyVHDLModel.DesignUnit.Entity.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in a package.
		   :meth:`IndexPackageBodies`
		     Index all declared items in a package body.
		   :meth:`IndexArchitectures`
		     Index all declared items in an architecture.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def IndexArchitectures(self) -> None:
		"""
		Index declared items in all architectures.

		.. rubric:: Algorithm

		1. Iterate all architectures:

		   * Index all declared items. |br|
		     |rarr| :meth:`pyVHDLModel.DesignUnit.Architecture.IndexDeclaredItems`

		.. seealso::

		   :meth:`IndexPackages`
		     Index all declared items in a package.
		   :meth:`IndexPackageBodies`
		     Index all declared items in a package body.
		   :meth:`IndexEntities`
		     Index all declared items in an entity.

		:raises UnhandledCriticalWarningError: If an identifier is declared twice in a declarative region and no
		                                       :class:`~pyTooling.Warning.WarningCollector` collects the
		                                       :exc:`~pyVHDLModel.Exception.DuplicateDeclarationWarning`.
		"""
		...

	def __repr__(self) -> str:
		"""
		Formats a representation of the library.

		**Format:** ``Library: 'my_library'``

		:returns: String representation of the library.
		"""
		...

	__str__ = __repr__

@export
class Document(ModelEntity, DocumentedEntityMixin):
	"""A ``Document`` represents a sourcefile. It contains *primary* and *secondary* design units."""

	_path:                   Path                                #: Path to the document.
	_vhdlVersion:            VHDLVersion                         #: VHDL version used for analyzing this source file.
	_library:                Library                             #: VHDL library used for analyzing the source file's content into.
	_designUnits:            list[DesignUnit]                    #: List of all design units defined in a document.
	_contexts:               dict[str, Context]                  #: Dictionary of all contexts defined in a document.
	_configurations:         dict[str, Configuration]            #: Dictionary of all configurations defined in a document.
	_entities:               dict[str, Entity]                   #: Dictionary of all entities defined in a document.
	_architectures:          dict[str, dict[str, Architecture]]  #: Dictionary of all architectures defined in a document.
	_packages:               dict[str, Package]                  #: Dictionary of all packages defined in a document.
	_packageBodies:          dict[str, PackageBody]              #: Dictionary of all package bodies defined in a document.
	_verificationUnits:      dict[str, VerificationUnit]         #: Dictionary of all PSL verification units defined in a document.
	_verificationProperties: dict[str, VerificationProperty]     #: Dictionary of all PSL verification properties defined in a document.
	_verificationModes:      dict[str, VerificationMode]         #: Dictionary of all PSL verification modes defined in a document.

	_dependencyVertex:       Vertex  #: Reference to the vertex in the dependency graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.
	_compileOrderVertex:     Vertex  #: Reference to the vertex in the compile-order graph representing the document. |br| This reference is set by :meth:`~pyVHDLModel.Design.CreateCompileOrderGraph`.

	def __init__(
		self,
		path:          Path,
		documentation: Nullable[str] = None,
		vhdlVersion:   VHDLVersion = VHDLVersion.VHDL2008,
		library:       Nullable[Library] = None,
		parent:        Nullable[ModelEntity] = None
	) -> None:
		"""
		Initializes a VHDL document.

		:param path:          Path to the document.
		:param documentation: The documentation comment associated with this declaration.
		:param vhdlVersion:   VHDL version used for analyzing this source file.
		:param library:       VHDL library used for analyzing the source file's content into.
		:param parent:        The parent model entity of this entity.
		:raises ValueError:   If parameter 'path' is None.
		:raises TypeError:    If parameter 'path' is not of type :class:`~pathlib.Path`.
		"""
		...

	def Visit(self, visitor: Visitor) -> None:
		"""
		Walk this document and its design units with a visitor.

		:param visitor: The visitor receiving the events.
		"""
		...

	def _AddEntity(self, item: Entity) -> None:
		"""
		Add an entity to the document's lists of design units.

		:param item:                Entity object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.Entity`.
		:raises VHDLModelException: If entity name already exists in document.
		"""
		...

	def _AddArchitecture(self, item: Architecture) -> None:
		"""
		Add an architecture to the document's lists of design units.

		:param item:                Architecture object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.Architecture`.
		:raises VHDLModelException: If architecture name already exists for the referenced entity name in document.
		"""
		...

	def _AddPackage(self, item: Package) -> None:
		"""
		Add a package to the document's lists of design units.

		:param item:                Package object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.Package`.
		:raises VHDLModelException: If package name already exists in document.
		"""
		...

	def _AddPackageBody(self, item: PackageBody) -> None:
		"""
		Add a package body to the document's lists of design units.

		:param item:                Package body object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.PackageBody`.
		:raises VHDLModelException: If package body name already exists in document.
		"""
		...

	def _AddContext(self, item: Context) -> None:
		"""
		Add a context to the document's lists of design units.

		:param item:                Context object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.Context`.
		:raises VHDLModelException: If context name already exists in document.
		"""
		...

	def _AddConfiguration(self, item: Configuration) -> None:
		"""
		Add a configuration to the document's lists of design units.

		:param item:                Configuration object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.Configuration`.
		:raises VHDLModelException: If configuration name already exists in document.
		"""
		...

	def _AddVerificationUnit(self, item: VerificationUnit) -> None:
		...

	def _AddVerificationProperty(self, item: VerificationProperty) -> None:
		...

	def _AddVerificationMode(self, item: VerificationMode) -> None:
		...

	def _AddDesignUnit(self, item: DesignUnit) -> None:
		"""
		Add a design unit to the document's lists of design units.

		:param item:                Configuration object to be added to the document.
		:raises TypeError:          If parameter 'item' is not of type :class:`~pyVHDLModel.DesignUnit.DesignUnit`.
		:raises ValueError:         If parameter 'item' is an unknown :class:`~pyVHDLModel.DesignUnit.DesignUnit`.
		:raises VHDLModelException: If configuration name already exists in document.
		"""
		...

	def AddDesignUnit(self, designUnit: DesignUnit) -> None:
		"""
		Add a design unit at the end of the document.

		The design unit's document is set to this document. If the document is registered in a design
		(:meth:`Design.AddDocument`), the design unit enters the document's library too.

		:param designUnit:                         The design unit to add.
		:raises ValueError:                        If parameter 'designUnit' is ``None``.
		:raises TypeError:                         If parameter 'designUnit' is not of type
		                                           :class:`~pyVHDLModel.DesignUnit.DesignUnit`.
		:raises AlreadyInDesignError:              If parameter 'designUnit' is already a design unit of a document.
		:raises DuplicateDesignUnitError:          If the document contains a design unit of the same kind and identifier.
		:raises EntityExistsInLibraryError:        If the library already contains an entity of the same identifier.
		:raises ArchitectureExistsInLibraryError:  If the library already contains an architecture of the same identifier
		                                           for the same entity.
		:raises PackageExistsInLibraryError:       If the library already contains a package of the same identifier.
		:raises PackageBodyExistsError:            If the library already contains a package body of the same identifier.
		:raises ConfigurationExistsInLibraryError: If the library already contains a configuration of the same identifier.
		:raises ContextExistsInLibraryError:       If the library already contains a context of the same identifier.

		.. seealso::

		   :meth:`InsertDesignUnit`
		      |rarr| Insert a design unit at a position of the document.
		   :meth:`RemoveDesignUnit`
		      |rarr| Remove a design unit from the document.
		"""
		...

	def InsertDesignUnit(self, index: int, designUnit: DesignUnit) -> None:
		"""
		Insert a design unit at a position of the document.

		The design units of a document are in source order. The design unit's document is set to this document. If the
		document is registered in a design (:meth:`Design.AddDocument`), the design unit enters the document's library too:
		the library becomes its parent. PSL verification units, properties and modes enter no library.

		:param index:                              Position, from ``0`` (first) to the number of design units (append).
		                                           A negative index counts from the end, as for :meth:`list.insert`.
		:param designUnit:                         The design unit to insert.
		:raises ValueError:                        If parameter 'index' is ``None``.
		:raises TypeError:                         If parameter 'index' is not of type :class:`int`.
		:raises ValueError:                        If parameter 'index' is out of range.
		:raises ValueError:                        If parameter 'designUnit' is ``None``.
		:raises TypeError:                         If parameter 'designUnit' is not of type
		                                           :class:`~pyVHDLModel.DesignUnit.DesignUnit`.
		:raises AlreadyInDesignError:              If parameter 'designUnit' is already a design unit of a document.
		:raises DuplicateDesignUnitError:          If the document contains a design unit of the same kind and identifier.
		:raises EntityExistsInLibraryError:        If the library already contains an entity of the same identifier.
		:raises ArchitectureExistsInLibraryError:  If the library already contains an architecture of the same identifier
		                                           for the same entity.
		:raises PackageExistsInLibraryError:       If the library already contains a package of the same identifier.
		:raises PackageBodyExistsError:            If the library already contains a package body of the same identifier.
		:raises ConfigurationExistsInLibraryError: If the library already contains a configuration of the same identifier.
		:raises ContextExistsInLibraryError:       If the library already contains a context of the same identifier.

		.. seealso::

		   :meth:`AddDesignUnit`
		      |rarr| Add a design unit at the end of the document.
		   :meth:`RemoveDesignUnit`
		      |rarr| Remove a design unit from the document.
		"""
		...

	def RemoveDesignUnit(self, designUnit: DesignUnit) -> None:
		"""
		Remove a design unit from the document.

		The design unit is detached: its document is cleared. If the document is registered in a design
		(:meth:`Design.AddDocument`), the design unit leaves the document's library too, and its parent is cleared. The
		design unit itself is unchanged and can be added to another document, or inserted at another position.

		:param designUnit:      The design unit to remove.
		:raises ValueError:     If parameter 'designUnit' is ``None``.
		:raises TypeError:      If parameter 'designUnit' is not of type :class:`~pyVHDLModel.DesignUnit.DesignUnit`.
		:raises NotAChildError: If parameter 'designUnit' is not a design unit of this document.

		.. seealso::

		   :meth:`AddDesignUnit`
		      |rarr| Add a design unit at the end of the document.
		   :meth:`InsertDesignUnit`
		      |rarr| Insert a design unit at a position of the document.
		"""
		...

	@readonly
	def Path(self) -> Path:
		"""
		Read-only property to access the document's path (:attr:`_path`).

		:returns: The path of this document.
		"""
		...

	@readonly
	def VHDLVersion(self) -> VHDLVersion:
		"""
		Read-only property to access the document's VHDL version (:attr:`_vhdlVersion`).

		:returns: VHDL version used to analyze this VHDL file.
		"""
		...

	@readonly
	def Library(self) -> Library:
		"""
		Read-only property to access the document's VHDL library (:attr:`_library`).

		:returns: VHDL library used to analyze the VHDL file's design units into.
		"""
		...

	@readonly
	def DesignUnits(self) -> list[DesignUnit]:
		"""
		Read-only property to access a list of all design units declarations found in this document (:attr:`_designUnits`).

		:returns: List of all design units.
		"""
		...

	@readonly
	def Contexts(self) -> dict[str, Context]:
		"""
		Read-only property to access the dictionary of all context declarations in this document (:attr:`_contexts`).

		:returns: Dictionary of all contexts, indexed by normalized identifier.
		"""
		...

	@readonly
	def Configurations(self) -> dict[str, Configuration]:
		"""
		Read-only property to access the dictionary of all configuration declarations in this document (:attr:`_configurations`).

		:returns: Dictionary of all configurations, indexed by normalized identifier.
		"""
		...

	@readonly
	def Entities(self) -> dict[str, Entity]:
		"""
		Read-only property to access the dictionary of all entity declarations in this document (:attr:`_entities`).

		:returns: Dictionary of all entities, indexed by normalized identifier.
		"""
		...

	@readonly
	def Architectures(self) -> dict[str, dict[str, Architecture]]:
		"""
		Read-only property to access the dictionary of all architecture declarations in this document (:attr:`_architectures`).

		:returns: Dictionary of all architectures, indexed by normalized entity identifier, then by normalized
		          architecture identifier.
		"""
		...

	@readonly
	def Packages(self) -> dict[str, Package]:
		"""
		Read-only property to access the dictionary of all package declarations in this document (:attr:`_packages`).

		:returns: Dictionary of all packages, indexed by normalized identifier.
		"""
		...

	@readonly
	def PackageBodies(self) -> dict[str, PackageBody]:
		"""
		Read-only property to access the dictionary of all package body declarations in this document (:attr:`_packageBodies`).

		:returns: Dictionary of all package bodies, indexed by normalized identifier.
		"""
		...

	@readonly
	def VerificationUnits(self) -> dict[str, VerificationUnit]:
		"""
		Read-only property to access the dictionary of all verification unit declarations in this document (:attr:`_verificationUnits`).

		:returns: Dictionary of all verification units, indexed by normalized identifier.
		"""
		...

	@readonly
	def VerificationProperties(self) -> dict[str, VerificationProperty]:
		"""
		Read-only property to access the dictionary of all verification property declarations in this document (:attr:`_verificationProperties`).

		:returns: Dictionary of all verification properties, indexed by normalized identifier.
		"""
		...

	@readonly
	def VerificationModes(self) -> dict[str, VerificationMode]:
		"""
		Read-only property to access the dictionary of all verification mode declarations in this document (:attr:`_verificationModes`).

		:returns: Dictionary of all verification mode declarations, indexed by normalized identifier.
		"""
		...

	@readonly
	def CompileOrderVertex(self) -> Vertex:
		"""
		Read-only property to access the corresponding compile-order vertex (:attr:`_compileOrderVertex`).

		The compile-order vertex references this document by its value field.

		:returns: The corresponding compile-order vertex.
		"""
		...

	def IterateDesignUnits(self, filter: DesignUnitKind = DesignUnitKind.All) -> Generator[DesignUnit, None, None]:
		"""
		Iterate all design units in the document.

		A union of :class:`DesignUnitKind` values can be given to filter the returned result for suitable design units.

		.. rubric:: Algorithm

		* If contexts are selected in the filter:

		  1. Iterate all contexts in that library.

		* If packages are selected in the filter:

		  1. Iterate all packages in that library.

		* If package bodies are selected in the filter:

		  1. Iterate all package bodies in that library.

		* If entites are selected in the filter:

		  1. Iterate all entites in that library.

		* If architectures are selected in the filter:

		  1. Iterate all architectures in that library.

		* If configurations are selected in the filter:

		  1. Iterate all configurations in that library.

		:param filter: An enumeration with possibly multiple flags to filter the returned design units.
		:returns:      A generator to iterate all matched design units in the document.

		.. seealso::

		   :meth:`pyVHDLModel.Design.IterateDesignUnits`
		     Iterate all design units in the design.
		   :meth:`pyVHDLModel.Library.IterateDesignUnits`
		     Iterate all design units in the library.
		"""
		...

	def __repr__(self) -> str:
		"""
		Formats a representation of the document.

		**Format:** ``Document: 'path/to/file.vhdl'``

		:returns: String representation of the document.
		"""
		...

	__str__ = __repr__