Code Coverage of pyVHDLModel: 66%

Files Functions Classes

coverage.py v7.15.1, created at 2026-07-13 17:58 +0000

      Statements   Branches   Total
File class   coverage statements missing excluded   coverage branches partial   coverage
pyVHDLModel/Association.py AssociationItem   0% 10 10 0   0% 4 0   0%
pyVHDLModel/Association.py (no class)   100% 20 0 0   100% 0 0   100%
pyVHDLModel/Base.py Direction   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Base.py Mode   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Base.py ModelEntity   44% 9 5 0   25% 4 1   38%
pyVHDLModel/Base.py NamedEntityMixin   100% 4 0 0   100% 0 0   100%
pyVHDLModel/Base.py OptionallyNamedEntityMixin   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Base.py MultipleNamedEntityMixin   75% 4 1 0   100% 0 0   75%
pyVHDLModel/Base.py LabeledEntityMixin   75% 4 1 0   100% 0 0   75%
pyVHDLModel/Base.py DocumentedEntityMixin   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Base.py ConditionalMixin   0% 4 4 0   0% 2 0   0%
pyVHDLModel/Base.py BranchMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Base.py ConditionalBranchMixin   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Base.py ReportStatementMixin   0% 8 8 0   0% 4 0   0%
pyVHDLModel/Base.py AssertStatementMixin   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Base.py BlockStatementMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Base.py Range   60% 10 4 0   100% 0 0   60%
pyVHDLModel/Base.py WaveformElement   0% 8 8 0   0% 2 0   0%
pyVHDLModel/Base.py (no class)   100% 113 0 0   100% 0 0   100%
pyVHDLModel/Common.py AllowBlackboxMixin   100% 5 0 0   100% 2 0   100%
pyVHDLModel/Common.py Statement   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Common.py ProcedureCallMixin   0% 9 9 0   0% 4 0   0%
pyVHDLModel/Common.py AssignmentMixin   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Common.py VariableAssignmentMixin   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Common.py (no class)   100% 37 0 0   100% 0 0   100%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin   68% 25 8 0   61% 18 3   65%
pyVHDLModel/Concurrent.py Instantiation   38% 13 8 0   25% 8 2   33%
pyVHDLModel/Concurrent.py ComponentInstantiation   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Concurrent.py EntityInstantiation   75% 8 2 0   50% 2 1   70%
pyVHDLModel/Concurrent.py ConfigurationInstantiation   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ProcessStatement   0% 10 10 0   0% 4 0   0%
pyVHDLModel/Concurrent.py ConcurrentProcedureCall   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ConcurrentBlockStatement   0% 18 18 0   0% 6 0   0%
pyVHDLModel/Concurrent.py GenerateBranch   0% 11 11 0   0% 2 0   0%
pyVHDLModel/Concurrent.py IfGenerateBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ElsifGenerateBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ElseGenerateBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py GenerateStatement   0% 2 2 2   100% 0 0   0%
pyVHDLModel/Concurrent.py IfGenerateStatement   0% 35 35 0   0% 20 0   0%
pyVHDLModel/Concurrent.py IndexedGenerateChoice   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Concurrent.py RangedGenerateChoice   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ConcurrentCase   0% 8 8 0   0% 2 0   0%
pyVHDLModel/Concurrent.py GenerateCase   0% 8 8 0   0% 4 0   0%
pyVHDLModel/Concurrent.py OthersGenerateCase   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Concurrent.py CaseGenerateStatement   0% 17 17 0   0% 10 0   0%
pyVHDLModel/Concurrent.py ForGenerateStatement   0% 16 16 0   0% 2 0   0%
pyVHDLModel/Concurrent.py ConcurrentSignalAssignment   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ConcurrentSimpleSignalAssignment   0% 7 7 0   0% 4 0   0%
pyVHDLModel/Concurrent.py ConcurrentSelectedSignalAssignment   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ConcurrentConditionalSignalAssignment   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Concurrent.py ConcurrentAssertStatement   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Concurrent.py (no class)   100% 163 0 0   100% 0 0   100%
pyVHDLModel/DesignUnit.py Reference   100% 3 0 0   100% 0 0   100%
pyVHDLModel/DesignUnit.py LibraryClause   100% 1 0 0   100% 0 0   100%
pyVHDLModel/DesignUnit.py DesignUnit   75% 36 9 0   90% 10 1   78%
pyVHDLModel/DesignUnit.py Context   67% 21 7 0   70% 10 1   68%
pyVHDLModel/DesignUnit.py Package   50% 22 11 0   0% 6 0   39%
pyVHDLModel/DesignUnit.py PackageBody   58% 12 5 0   100% 0 0   58%
pyVHDLModel/DesignUnit.py Entity   73% 15 4 0   100% 0 0   73%
pyVHDLModel/DesignUnit.py Architecture   57% 14 6 0   100% 0 0   57%
pyVHDLModel/DesignUnit.py Component   0% 27 27 0   0% 12 0   0%
pyVHDLModel/DesignUnit.py Configuration   33% 6 4 0   100% 0 0   33%
pyVHDLModel/DesignUnit.py (no class)   100% 130 0 0   100% 0 0   100%
pyVHDLModel/Exception.py LibraryExistsInDesignError   67% 3 1 0   100% 0 0   67%
pyVHDLModel/Exception.py LibraryRegisteredToForeignDesignError   67% 3 1 0   100% 0 0   67%
pyVHDLModel/Exception.py LibraryNotRegisteredError   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Exception.py EntityExistsInLibraryError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError   0% 7 7 0   100% 0 0   0%
pyVHDLModel/Exception.py PackageExistsInLibraryError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py PackageBodyExistsError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py ConfigurationExistsInLibraryError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py ContextExistsInLibraryError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py ReferencedLibraryNotExistingError   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Exception.py (no class)   100% 83 0 0   100% 0 0   100%
pyVHDLModel/Expression.py NullLiteral   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Expression.py EnumerationLiteral   50% 4 2 0   100% 0 0   50%
pyVHDLModel/Expression.py IntegerLiteral   50% 4 2 0   100% 0 0   50%
pyVHDLModel/Expression.py FloatingPointLiteral   50% 4 2 0   100% 0 0   50%
pyVHDLModel/Expression.py PhysicalLiteral   50% 4 2 0   100% 0 0   50%
pyVHDLModel/Expression.py PhysicalIntegerLiteral   67% 3 1 0   100% 0 0   67%
pyVHDLModel/Expression.py PhysicalFloatingLiteral   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Expression.py CharacterLiteral   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Expression.py StringLiteral   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Expression.py BitStringLiteral   0% 24 24 0   0% 10 0   0%
pyVHDLModel/Expression.py ParenthesisExpression   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Expression.py UnaryExpression   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Expression.py BinaryExpression   0% 8 8 0   100% 0 0   0%
pyVHDLModel/Expression.py RangeExpression   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Expression.py QualifiedExpression   0% 8 8 0   100% 0 0   0%
pyVHDLModel/Expression.py TernaryExpression   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Expression.py SubtypeAllocation   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Expression.py QualifiedExpressionAllocation   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Expression.py AggregateElement   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Expression.py SimpleAggregateElement   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Expression.py IndexedAggregateElement   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Expression.py RangedAggregateElement   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Expression.py NamedAggregateElement   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Expression.py OthersAggregateElement   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Expression.py Aggregate   0% 8 8 0   0% 2 0   0%
pyVHDLModel/Expression.py (no class)   100% 355 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Ieee   71% 24 7 0   71% 14 4   71%
pyVHDLModel/IEEE.py Math_Complex   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Math_Complex_Body   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_1164   100% 16 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_TextIO   100% 4 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Numeric_Bit   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Numeric_Bit_Unsigned_Body   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Numeric_Std   100% 18 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Numeric_Std_Unsigned   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Numeric_Std_Unsigned_Body   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg   100% 6 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg_Body   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Fixed_Pkg   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Float_Generic_Pkg   100% 6 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Float_Pkg   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_Arith   100% 2 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py VITAL_Timing   0% 3 3 0   100% 0 0   0%
pyVHDLModel/IEEE.py VITAL_Timing_Body   0% 3 3 0   100% 0 0   0%
pyVHDLModel/IEEE.py VITAL_Primitives   0% 4 4 0   100% 0 0   0%
pyVHDLModel/IEEE.py VITAL_Primitives_Body   0% 3 3 0   100% 0 0   0%
pyVHDLModel/IEEE.py VITAL_Memory   0% 7 7 0   100% 0 0   0%
pyVHDLModel/IEEE.py VITAL_Memory_Body   0% 7 7 0   100% 0 0   0%
pyVHDLModel/IEEE.py Std_Logic_Arith   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_Misc   100% 3 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_Signed   100% 4 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_TextIO   100% 4 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py Std_Logic_Unsigned   100% 4 0 0   100% 0 0   100%
pyVHDLModel/IEEE.py (no class)   100% 119 0 0   100% 0 0   100%
pyVHDLModel/Instantiation.py GenericInstantiationMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Instantiation.py GenericEntityInstantiationMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Instantiation.py SubprogramInstantiationMixin   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Instantiation.py PackageInstantiation   0% 12 12 0   0% 4 0   0%
pyVHDLModel/Instantiation.py (no class)   100% 32 0 0   100% 0 0   100%
pyVHDLModel/Interface.py InterfaceItemMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Interface.py InterfaceItemWithModeMixin   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py PortInterfaceItemMixin   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericConstantInterfaceItem   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericTypeInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericProcedureInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericFunctionInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py InterfacePackage   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericPackageInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py PortSignalInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py ParameterConstantInterfaceItem   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py ParameterVariableInterfaceItem   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py ParameterSignalInterfaceItem   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py ParameterFileInterfaceItem   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Interface.py WithGenericsMixin   43% 7 4 0   25% 4 1   36%
pyVHDLModel/Interface.py WithPortsMixin   43% 7 4 0   25% 4 1   36%
pyVHDLModel/Interface.py WithParametersMixin   0% 7 7 0   0% 4 0   0%
pyVHDLModel/Interface.py InterfaceGroup   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Interface.py GenericGroup   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Interface.py PortGroup   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Interface.py ParameterGroup   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Interface.py (no class)   100% 102 0 0   100% 0 0   100%
pyVHDLModel/Name.py Name   100% 15 0 0   100% 2 0   100%
pyVHDLModel/Name.py ParenthesisName   0% 7 7 0   0% 2 0   0%
pyVHDLModel/Name.py IndexedName   0% 7 7 0   0% 2 0   0%
pyVHDLModel/Name.py SelectedName   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Name.py AttributeName   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Name.py AllName   100% 1 0 0   100% 0 0   100%
pyVHDLModel/Name.py OpenName   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Name.py (no class)   100% 50 0 0   100% 0 0   100%
pyVHDLModel/Namespace.py ExtendedKeyError   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Namespace.py Namespace   7% 61 57 0   0% 30 0   4%
pyVHDLModel/Namespace.py (no class)   100% 23 0 0   100% 0 0   100%
pyVHDLModel/Object.py Obj   75% 8 2 0   100% 0 0   75%
pyVHDLModel/Object.py WithDefaultExpressionMixin   50% 4 2 0   50% 2 1   50%
pyVHDLModel/Object.py Constant   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Object.py DeferredConstant   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Object.py Variable   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Object.py Signal   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Object.py (no class)   100% 39 0 0   100% 0 0   100%
pyVHDLModel/PSLModel.py VerificationUnit   0% 1 1 0   100% 0 0   0%
pyVHDLModel/PSLModel.py VerificationProperty   0% 1 1 0   100% 0 0   0%
pyVHDLModel/PSLModel.py VerificationMode   0% 1 1 0   100% 0 0   0%
pyVHDLModel/PSLModel.py DefaultClock   0% 2 2 0   100% 0 0   0%
pyVHDLModel/PSLModel.py (no class)   100% 21 0 0   100% 0 0   100%
pyVHDLModel/Predefined.py PredefinedLibrary   100% 10 0 0   100% 4 0   100%
pyVHDLModel/Predefined.py PredefinedPackageMixin   93% 14 1 0   75% 4 1   89%
pyVHDLModel/Predefined.py PredefinedPackage   100% 1 0 0   100% 0 0   100%
pyVHDLModel/Predefined.py PredefinedPackageBody   100% 2 0 0   100% 0 0   100%
pyVHDLModel/Predefined.py (no class)   100% 21 0 0   100% 0 0   100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin   36% 61 39 0   18% 34 2   29%
pyVHDLModel/Regions.py (no class)   100% 31 0 0   100% 0 0   100%
pyVHDLModel/STD.py Std   100% 1 0 0   100% 0 0   100%
pyVHDLModel/STD.py Standard   100% 60 0 0   100% 0 0   100%
pyVHDLModel/STD.py Env   100% 2 0 0   100% 0 0   100%
pyVHDLModel/STD.py (no class)   100% 25 0 0   100% 0 0   100%
pyVHDLModel/Sequential.py SequentialStatementsMixin   0% 6 6 0   0% 4 0   0%
pyVHDLModel/Sequential.py SequentialProcedureCall   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py SequentialSignalAssignment   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py SequentialSimpleSignalAssignment   0% 7 7 0   0% 4 0   0%
pyVHDLModel/Sequential.py SequentialVariableAssignment   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py SequentialReportStatement   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py SequentialAssertStatement   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py Branch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py IfBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py ElsifBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py ElseBranch   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py IfStatement   0% 15 15 0   0% 6 0   0%
pyVHDLModel/Sequential.py IndexedChoice   0% 4 4 0   100% 0 0   0%
pyVHDLModel/Sequential.py RangedChoice   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Sequential.py SequentialCase   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Sequential.py Case   0% 8 8 0   0% 4 0   0%
pyVHDLModel/Sequential.py OthersCase   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Sequential.py CaseStatement   0% 10 10 0   0% 4 0   0%
pyVHDLModel/Sequential.py LoopStatement   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py ForLoopStatement   0% 6 6 0   100% 0 0   0%
pyVHDLModel/Sequential.py WhileLoopStatement   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Sequential.py LoopControlStatement   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Sequential.py ReturnStatement   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Sequential.py WaitStatement   0% 13 13 0   0% 6 0   0%
pyVHDLModel/Sequential.py SequentialDeclarationsMixin   0% 6 6 0   0% 4 0   0%
pyVHDLModel/Sequential.py (no class)   100% 141 0 0   100% 0 0   100%
pyVHDLModel/Subprogram.py Subprogram   0% 13 13 0   100% 0 0   0%
pyVHDLModel/Subprogram.py Procedure   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Subprogram.py Function   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Subprogram.py MethodMixin   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Subprogram.py ProcedureMethod   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Subprogram.py FunctionMethod   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Subprogram.py (no class)   100% 38 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py Symbol   92% 13 1 0   100% 4 0   94%
pyVHDLModel/Symbol.py LibraryReferenceSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py PackageReferenceSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py ContextReferenceSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py PackageMemberReferenceSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py AllPackageMembersReferenceSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py EntityInstantiationSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py ComponentInstantiationSymbol   33% 3 2 0   100% 0 0   33%
pyVHDLModel/Symbol.py ConfigurationInstantiationSymbol   33% 3 2 0   100% 0 0   33%
pyVHDLModel/Symbol.py EntitySymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py ArchitectureSymbol   0% 3 3 0   100% 0 0   0%
pyVHDLModel/Symbol.py PackageSymbol   100% 3 0 0   100% 0 0   100%
pyVHDLModel/Symbol.py RecordElementSymbol   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Symbol.py SubtypeSymbol   33% 3 2 0   100% 0 0   33%
pyVHDLModel/Symbol.py ArrayConstraint   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Symbol.py RecordConstraint   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Symbol.py ConstrainedArraySubtypeSymbol   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Symbol.py ConstrainedRecordSubtypeSymbol   0% 2 2 0   100% 0 0   0%
pyVHDLModel/Symbol.py SimpleObjectOrFunctionCallSymbol   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Symbol.py IndexedObjectOrFunctionCallSymbol   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Symbol.py (no class)   100% 178 0 0   100% 0 0   100%
pyVHDLModel/Type.py BaseType   100% 4 0 0   100% 0 0   100%
pyVHDLModel/Type.py Subtype   50% 10 5 0   100% 0 0   50%
pyVHDLModel/Type.py RangedScalarType   67% 3 1 0   100% 0 0   67%
pyVHDLModel/Type.py NumericTypeMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Type.py DiscreteTypeMixin   0% 1 1 0   100% 0 0   0%
pyVHDLModel/Type.py EnumeratedType   75% 8 2 0   75% 4 1   75%
pyVHDLModel/Type.py IntegerType   50% 2 1 0   100% 0 0   50%
pyVHDLModel/Type.py RealType   50% 2 1 0   100% 0 0   50%
pyVHDLModel/Type.py PhysicalType   67% 9 3 0   100% 2 0   73%
pyVHDLModel/Type.py ArrayType   62% 8 3 0   100% 2 0   70%
pyVHDLModel/Type.py RecordTypeElement   0% 6 6 0   100% 0 0   0%
pyVHDLModel/Type.py RecordType   50% 8 4 0   50% 4 2   50%
pyVHDLModel/Type.py ProtectedType   0% 7 7 0   0% 4 0   0%
pyVHDLModel/Type.py ProtectedTypeBody   0% 7 7 0   0% 4 0   0%
pyVHDLModel/Type.py AccessType   60% 5 2 0   100% 0 0   60%
pyVHDLModel/Type.py FileType   0% 5 5 0   100% 0 0   0%
pyVHDLModel/Type.py (no class)   100% 111 0 0   100% 0 0   100%
pyVHDLModel/__init__.py VHDLVersion   7% 42 39 0   14% 28 0   10%
pyVHDLModel/__init__.py ObjectClass   0% 1 1 0   100% 0 0   0%
pyVHDLModel/__init__.py Design   59% 583 241 0   53% 316 29   57%
pyVHDLModel/__init__.py Library   66% 95 32 0   75% 60 5   70%
pyVHDLModel/__init__.py Document   60% 160 64 22   52% 82 19   57%
pyVHDLModel/__init__.py (no class)   100% 274 0 0   100% 0 0   100%
Total     70% 4407 1304 24   42% 806 75   66%

No items found using the specified filter.

136 empty classes skipped.