Code Coverage of pyVHDLModel: 73%

Files Functions Classes

coverage.py v7.6.7, created at 2024-11-22 22:15 +0000

File class statements missing excluded branches partial coverage
pyVHDLModel/Association.py AssociationItem 10 10 0 4 0 0%
pyVHDLModel/Association.py (no class) 22 0 0 0 0 100%
pyVHDLModel/Base.py Direction 1 0 0 0 0 100%
pyVHDLModel/Base.py Mode 1 1 0 0 0 0%
pyVHDLModel/Base.py ModelEntity 6 4 0 2 0 25%
pyVHDLModel/Base.py NamedEntityMixin 4 0 0 0 0 100%
pyVHDLModel/Base.py MultipleNamedEntityMixin 4 1 0 0 0 75%
pyVHDLModel/Base.py LabeledEntityMixin 4 1 0 0 0 75%
pyVHDLModel/Base.py DocumentedEntityMixin 2 0 0 0 0 100%
pyVHDLModel/Base.py ConditionalMixin 4 4 0 2 0 0%
pyVHDLModel/Base.py BranchMixin 1 1 0 0 0 0%
pyVHDLModel/Base.py ConditionalBranchMixin 2 2 0 0 0 0%
pyVHDLModel/Base.py ReportStatementMixin 8 8 0 4 0 0%
pyVHDLModel/Base.py AssertStatementMixin 2 2 0 0 0 0%
pyVHDLModel/Base.py BlockStatementMixin 1 1 0 0 0 0%
pyVHDLModel/Base.py Range 10 1 0 0 0 90%
pyVHDLModel/Base.py WaveformElement 8 8 0 2 0 0%
pyVHDLModel/Base.py (no class) 120 0 0 0 0 100%
pyVHDLModel/Common.py Statement 2 0 0 0 0 100%
pyVHDLModel/Common.py ProcedureCallMixin 9 9 0 4 0 0%
pyVHDLModel/Common.py AssignmentMixin 3 3 0 0 0 0%
pyVHDLModel/Common.py VariableAssignmentMixin 4 4 0 0 0 0%
pyVHDLModel/Common.py (no class) 34 0 0 0 0 100%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin 25 8 0 18 3 65%
pyVHDLModel/Concurrent.py Instantiation 13 8 0 8 2 33%
pyVHDLModel/Concurrent.py ComponentInstantiation 4 4 0 0 0 0%
pyVHDLModel/Concurrent.py EntityInstantiation 8 2 0 2 1 70%
pyVHDLModel/Concurrent.py ConfigurationInstantiation 4 4 0 0 0 0%
pyVHDLModel/Concurrent.py ProcessStatement 10 10 0 4 0 0%
pyVHDLModel/Concurrent.py ConcurrentProcedureCall 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentBlockStatement 12 12 0 4 0 0%
pyVHDLModel/Concurrent.py GenerateBranch 8 8 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateBranch 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ElsifGenerateBranch 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ElseGenerateBranch 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateStatement 2 2 2 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement 25 25 0 14 0 0%
pyVHDLModel/Concurrent.py IndexedGenerateChoice 5 5 0 0 0 0%
pyVHDLModel/Concurrent.py RangedGenerateChoice 5 5 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentCase 4 4 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateCase 8 8 0 4 0 0%
pyVHDLModel/Concurrent.py OthersGenerateCase 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement 14 14 0 8 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement 11 11 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentSignalAssignment 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentSimpleSignalAssignment 7 7 0 4 0 0%
pyVHDLModel/Concurrent.py ConcurrentSelectedSignalAssignment 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentConditionalSignalAssignment 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentAssertStatement 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py (no class) 183 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Reference 3 0 0 0 0 100%
pyVHDLModel/DesignUnit.py LibraryClause 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit 36 9 0 10 1 78%
pyVHDLModel/DesignUnit.py Context 21 7 0 10 1 68%
pyVHDLModel/DesignUnit.py Package 26 15 0 10 1 33%
pyVHDLModel/DesignUnit.py PackageBody 12 5 0 0 0 58%
pyVHDLModel/DesignUnit.py Entity 24 10 0 8 2 50%
pyVHDLModel/DesignUnit.py Architecture 13 6 0 0 0 54%
pyVHDLModel/DesignUnit.py Component 17 17 0 8 0 0%
pyVHDLModel/DesignUnit.py Configuration 6 4 0 0 0 33%
pyVHDLModel/DesignUnit.py (no class) 156 0 0 0 0 100%
pyVHDLModel/Exception.py LibraryExistsInDesignError 3 1 0 0 0 67%
pyVHDLModel/Exception.py LibraryRegisteredToForeignDesignError 3 1 0 0 0 67%
pyVHDLModel/Exception.py LibraryNotRegisteredError 3 3 0 0 0 0%
pyVHDLModel/Exception.py EntityExistsInLibraryError 5 5 0 0 0 0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError 7 7 0 0 0 0%
pyVHDLModel/Exception.py PackageExistsInLibraryError 5 5 0 0 0 0%
pyVHDLModel/Exception.py PackageBodyExistsError 5 5 0 0 0 0%
pyVHDLModel/Exception.py ConfigurationExistsInLibraryError 5 5 0 0 0 0%
pyVHDLModel/Exception.py ContextExistsInLibraryError 5 5 0 0 0 0%
pyVHDLModel/Exception.py ReferencedLibraryNotExistingError 5 5 0 0 0 0%
pyVHDLModel/Exception.py (no class) 91 0 2 0 0 100%
pyVHDLModel/Expression.py NullLiteral 1 1 0 0 0 0%
pyVHDLModel/Expression.py EnumerationLiteral 4 1 0 0 0 75%
pyVHDLModel/Expression.py IntegerLiteral 4 1 0 0 0 75%
pyVHDLModel/Expression.py FloatingPointLiteral 4 2 0 0 0 50%
pyVHDLModel/Expression.py PhysicalLiteral 4 1 0 0 0 75%
pyVHDLModel/Expression.py PhysicalIntegerLiteral 3 1 0 0 0 67%
pyVHDLModel/Expression.py PhysicalFloatingLiteral 3 3 0 0 0 0%
pyVHDLModel/Expression.py CharacterLiteral 4 4 0 0 0 0%
pyVHDLModel/Expression.py StringLiteral 4 4 0 0 0 0%
pyVHDLModel/Expression.py BitStringLiteral 4 4 0 0 0 0%
pyVHDLModel/Expression.py ParenthesisExpression 1 1 0 0 0 0%
pyVHDLModel/Expression.py UnaryExpression 4 4 0 0 0 0%
pyVHDLModel/Expression.py BinaryExpression 8 8 0 0 0 0%
pyVHDLModel/Expression.py RangeExpression 1 1 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpression 8 8 0 0 0 0%
pyVHDLModel/Expression.py TernaryExpression 5 5 0 0 0 0%
pyVHDLModel/Expression.py SubtypeAllocation 5 5 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpressionAllocation 5 5 0 0 0 0%
pyVHDLModel/Expression.py AggregateElement 4 4 0 0 0 0%
pyVHDLModel/Expression.py SimpleAggregateElement 1 1 0 0 0 0%
pyVHDLModel/Expression.py IndexedAggregateElement 4 4 0 0 0 0%
pyVHDLModel/Expression.py RangedAggregateElement 5 5 0 0 0 0%
pyVHDLModel/Expression.py NamedAggregateElement 5 5 0 0 0 0%
pyVHDLModel/Expression.py OthersAggregateElement 1 1 0 0 0 0%
pyVHDLModel/Expression.py Aggregate 8 8 0 2 0 0%
pyVHDLModel/Expression.py (no class) 353 0 0 0 0 100%
pyVHDLModel/IEEE.py Ieee 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Math_Complex 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Math_Complex_Body 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Std_logic_1164 16 0 0 0 0 100%
pyVHDLModel/IEEE.py std_logic_textio 4 0 0 0 0 100%
pyVHDLModel/IEEE.py Std_logic_misc 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Bit 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Bit_Unsigned_Body 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Std 18 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Std_Unsigned 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Std_Unsigned_Body 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg 6 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg_Body 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Pkg 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Float_Generic_Pkg 6 0 0 0 0 100%
pyVHDLModel/IEEE.py Float_Pkg 2 0 0 0 0 100%
pyVHDLModel/IEEE.py (no class) 75 0 0 0 0 100%
pyVHDLModel/Instantiation.py GenericInstantiationMixin 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py GenericEntityInstantiationMixin 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py SubprogramInstantiationMixin 2 2 0 0 0 0%
pyVHDLModel/Instantiation.py PackageInstantiation 6 6 0 0 0 0%
pyVHDLModel/Instantiation.py (no class) 33 0 0 0 0 100%
pyVHDLModel/Interface.py InterfaceItemMixin 1 1 0 0 0 0%
pyVHDLModel/Interface.py InterfaceItemWithModeMixin 2 2 0 0 0 0%
pyVHDLModel/Interface.py PortInterfaceItemMixin 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericConstantInterfaceItem 3 3 0 0 0 0%
pyVHDLModel/Interface.py GenericTypeInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericProcedureInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericFunctionInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericPackageInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py PortSignalInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py ParameterConstantInterfaceItem 3 3 0 0 0 0%
pyVHDLModel/Interface.py ParameterVariableInterfaceItem 3 3 0 0 0 0%
pyVHDLModel/Interface.py ParameterSignalInterfaceItem 3 3 0 0 0 0%
pyVHDLModel/Interface.py ParameterFileInterfaceItem 2 2 0 0 0 0%
pyVHDLModel/Interface.py (no class) 57 0 0 0 0 100%
pyVHDLModel/Name.py Name 15 0 0 2 0 100%
pyVHDLModel/Name.py ParenthesisName 7 7 0 2 0 0%
pyVHDLModel/Name.py IndexedName 7 7 0 2 0 0%
pyVHDLModel/Name.py SelectedName 2 0 0 0 0 100%
pyVHDLModel/Name.py AttributeName 2 0 0 0 0 100%
pyVHDLModel/Name.py AllName 1 0 0 0 0 100%
pyVHDLModel/Name.py OpenName 2 2 0 0 0 0%
pyVHDLModel/Name.py (no class) 56 0 0 0 0 100%
pyVHDLModel/Namespace.py Namespace 59 47 0 30 3 19%
pyVHDLModel/Namespace.py (no class) 25 0 0 0 0 100%
pyVHDLModel/Object.py Obj 8 2 0 0 0 75%
pyVHDLModel/Object.py WithDefaultExpressionMixin 4 2 0 2 1 50%
pyVHDLModel/Object.py Constant 2 0 0 0 0 100%
pyVHDLModel/Object.py DeferredConstant 3 3 0 0 0 0%
pyVHDLModel/Object.py Variable 2 2 0 0 0 0%
pyVHDLModel/Object.py Signal 2 0 0 0 0 100%
pyVHDLModel/Object.py (no class) 43 0 0 0 0 100%
pyVHDLModel/PSLModel.py VerificationUnit 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py VerificationProperty 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py VerificationMode 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py DefaultClock 2 2 0 0 0 0%
pyVHDLModel/PSLModel.py (no class) 21 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedLibrary 10 0 0 4 0 100%
pyVHDLModel/Predefined.py PredefinedPackageMixin 14 1 0 4 1 89%
pyVHDLModel/Predefined.py PredefinedPackage 1 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedPackageBody 2 0 0 0 0 100%
pyVHDLModel/Predefined.py (no class) 21 0 0 0 0 100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin 55 35 0 32 2 30%
pyVHDLModel/Regions.py (no class) 38 0 0 0 0 100%
pyVHDLModel/STD.py Std 1 0 0 0 0 100%
pyVHDLModel/STD.py Standard 54 0 0 0 0 100%
pyVHDLModel/STD.py Env 2 0 0 0 0 100%
pyVHDLModel/STD.py (no class) 25 0 0 0 0 100%
pyVHDLModel/Sequential.py SequentialStatementsMixin 6 6 0 4 0 0%
pyVHDLModel/Sequential.py SequentialProcedureCall 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialSignalAssignment 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialSimpleSignalAssignment 7 7 0 4 0 0%
pyVHDLModel/Sequential.py SequentialVariableAssignment 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialReportStatement 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialAssertStatement 2 2 0 0 0 0%
pyVHDLModel/Sequential.py Branch 2 2 0 0 0 0%
pyVHDLModel/Sequential.py IfBranch 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ElsifBranch 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ElseBranch 2 2 0 0 0 0%
pyVHDLModel/Sequential.py IfStatement 15 15 0 6 0 0%
pyVHDLModel/Sequential.py IndexedChoice 4 4 0 0 0 0%
pyVHDLModel/Sequential.py RangedChoice 5 5 0 0 0 0%
pyVHDLModel/Sequential.py SequentialCase 3 3 0 0 0 0%
pyVHDLModel/Sequential.py Case 8 8 0 4 0 0%
pyVHDLModel/Sequential.py OthersCase 1 1 0 0 0 0%
pyVHDLModel/Sequential.py CaseStatement 10 10 0 4 0 0%
pyVHDLModel/Sequential.py LoopStatement 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ForLoopStatement 6 6 0 0 0 0%
pyVHDLModel/Sequential.py WhileLoopStatement 2 2 0 0 0 0%
pyVHDLModel/Sequential.py LoopControlStatement 3 3 0 0 0 0%
pyVHDLModel/Sequential.py ReturnStatement 3 3 0 0 0 0%
pyVHDLModel/Sequential.py WaitStatement 13 13 0 6 0 0%
pyVHDLModel/Sequential.py SequentialDeclarationsMixin 6 6 0 4 0 0%
pyVHDLModel/Sequential.py (no class) 158 0 0 0 0 100%
pyVHDLModel/Subprogram.py Subprogram 13 13 0 0 0 0%
pyVHDLModel/Subprogram.py Procedure 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Function 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py MethodMixin 3 3 0 0 0 0%
pyVHDLModel/Subprogram.py ProcedureMethod 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py FunctionMethod 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py (no class) 45 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol 13 1 0 4 0 94%
pyVHDLModel/Symbol.py LibraryReferenceSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageReferenceSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py ContextReferenceSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageMemberReferenceSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py AllPackageMembersReferenceSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py EntityInstantiationSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py ComponentInstantiationSymbol 3 2 0 0 0 33%
pyVHDLModel/Symbol.py ConfigurationInstantiationSymbol 3 2 0 0 0 33%
pyVHDLModel/Symbol.py EntitySymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py ArchitectureSymbol 3 3 0 0 0 0%
pyVHDLModel/Symbol.py PackageSymbol 3 0 0 0 0 100%
pyVHDLModel/Symbol.py RecordElementSymbol 1 1 0 0 0 0%
pyVHDLModel/Symbol.py SubtypeSymbol 3 2 0 0 0 33%
pyVHDLModel/Symbol.py SimpleObjectOrFunctionCallSymbol 1 1 0 0 0 0%
pyVHDLModel/Symbol.py IndexedObjectOrFunctionCallSymbol 1 1 0 0 0 0%
pyVHDLModel/Symbol.py (no class) 168 0 0 0 0 100%
pyVHDLModel/Type.py BaseType 4 0 0 0 0 100%
pyVHDLModel/Type.py Subtype 10 4 0 0 0 60%
pyVHDLModel/Type.py RangedScalarType 3 0 0 0 0 100%
pyVHDLModel/Type.py NumericTypeMixin 1 1 0 0 0 0%
pyVHDLModel/Type.py DiscreteTypeMixin 1 1 0 0 0 0%
pyVHDLModel/Type.py EnumeratedType 8 1 0 4 1 83%
pyVHDLModel/Type.py IntegerType 2 0 0 0 0 100%
pyVHDLModel/Type.py RealType 2 1 0 0 0 50%
pyVHDLModel/Type.py PhysicalType 9 2 0 2 0 82%
pyVHDLModel/Type.py ArrayType 8 2 0 2 0 80%
pyVHDLModel/Type.py RecordTypeElement 6 6 0 0 0 0%
pyVHDLModel/Type.py RecordType 8 4 0 4 2 50%
pyVHDLModel/Type.py ProtectedType 7 7 0 4 0 0%
pyVHDLModel/Type.py ProtectedTypeBody 7 7 0 4 0 0%
pyVHDLModel/Type.py AccessType 5 5 0 0 0 0%
pyVHDLModel/Type.py FileType 5 5 0 0 0 0%
pyVHDLModel/Type.py (no class) 130 0 0 0 0 100%
pyVHDLModel/__init__.py VHDLVersion 42 39 0 28 0 10%
pyVHDLModel/__init__.py ObjectClass 1 1 0 0 0 0%
pyVHDLModel/__init__.py Design 529 125 3 276 37 77%
pyVHDLModel/__init__.py Library 69 5 0 50 4 92%
pyVHDLModel/__init__.py Document 156 62 22 82 14 60%
pyVHDLModel/__init__.py (no class) 278 0 0 0 0 100%
Total   4149 992 33 702 76 73%

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126 empty classes skipped.