| pyVHDLModel/Association.py |
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0 |
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1 |
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| pyVHDLModel/Association.py |
GenericMapAspectMixin |
|
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| pyVHDLModel/Association.py |
PortMapAspectMixin |
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84% |
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| pyVHDLModel/Association.py |
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AllowBlackboxMixin |
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Statement |
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| pyVHDLModel/Common.py |
ProcedureCallMixin |
|
91% |
74 |
7 |
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89% |
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5 |
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90% |
| pyVHDLModel/Common.py |
AssignmentMixin |
|
100% |
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SignalAssignmentMixin |
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VariableAssignmentMixin |
|
80% |
5 |
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| pyVHDLModel/Common.py |
WaveformMixin |
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ExpressionMixin |
|
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3 |
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ConditionalWaveform |
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ConditionalExpression |
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ConditionalWaveformsMixin |
|
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| pyVHDLModel/Common.py |
SelectedWaveform |
|
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|
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SelectedExpressionsMixin |
|
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| pyVHDLModel/Common.py |
(no class) |
|
99% |
115 |
1 |
0 |
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50% |
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98% |
| pyVHDLModel/Concurrent.py |
ConcurrentStatementsMixin |
|
82% |
164 |
30 |
0 |
|
77% |
106 |
22 |
|
80% |
| pyVHDLModel/Concurrent.py |
Instantiation |
|
100% |
5 |
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0 |
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ComponentInstantiation |
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ConfigurationInstantiation |
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ProcessStatement |
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ConcurrentProcedureCall |
|
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| pyVHDLModel/Concurrent.py |
ConcurrentBlockStatement |
|
93% |
27 |
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| pyVHDLModel/Concurrent.py |
GenerateBranch |
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| pyVHDLModel/Concurrent.py |
IfGenerateBranch |
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GenerateStatement |
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2 |
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IfGenerateStatement |
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3 |
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| pyVHDLModel/Concurrent.py |
IndexedGenerateChoice |
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| pyVHDLModel/Concurrent.py |
GenerateCase |
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| pyVHDLModel/Concurrent.py |
CaseGenerateStatement |
|
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23 |
0 |
0 |
|
92% |
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1 |
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| pyVHDLModel/Concurrent.py |
ForGenerateStatement |
|
95% |
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1 |
0 |
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| pyVHDLModel/Concurrent.py |
ConcurrentSignalAssignment |
|
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| pyVHDLModel/Concurrent.py |
ConcurrentSimpleSignalAssignment |
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| pyVHDLModel/Concurrent.py |
ConcurrentSelectedSignalAssignment |
|
100% |
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| pyVHDLModel/Concurrent.py |
ConcurrentConditionalSignalAssignment |
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| pyVHDLModel/Concurrent.py |
ConcurrentAssertStatement |
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| pyVHDLModel/Concurrent.py |
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EntityAspectConfiguration |
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| pyVHDLModel/Configuration.py |
EntityAspectOpen |
|
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BindingIndication |
|
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94% |
| pyVHDLModel/Configuration.py |
AllInstantiationList |
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ComponentConfiguration |
|
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| pyVHDLModel/Declaration.py |
Attribute |
|
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10 |
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| pyVHDLModel/Declaration.py |
AttributeSpecification |
|
88% |
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Alias |
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| pyVHDLModel/DesignUnit.py |
Reference |
|
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LibraryClause |
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UseClause |
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ContextReference |
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| pyVHDLModel/DesignUnit.py |
DesignUnit |
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93 |
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2 |
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| pyVHDLModel/DesignUnit.py |
Context |
|
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2 |
0 |
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100% |
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0 |
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94% |
| pyVHDLModel/DesignUnit.py |
Package |
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84% |
37 |
6 |
0 |
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58% |
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3 |
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| pyVHDLModel/DesignUnit.py |
PackageBody |
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4 |
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| pyVHDLModel/DesignUnit.py |
Entity |
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28 |
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| pyVHDLModel/DesignUnit.py |
Architecture |
|
88% |
24 |
3 |
0 |
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100% |
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| pyVHDLModel/DesignUnit.py |
Component |
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90% |
20 |
2 |
0 |
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100% |
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| pyVHDLModel/DesignUnit.py |
Configuration |
|
79% |
19 |
4 |
0 |
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100% |
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79% |
| pyVHDLModel/DesignUnit.py |
(no class) |
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99% |
192 |
1 |
0 |
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50% |
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NotImplementedWarning |
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100% |
3 |
0 |
0 |
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100% |
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DuplicateDeclarationWarning |
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100% |
11 |
0 |
0 |
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100% |
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| pyVHDLModel/Exception.py |
BlackboxWarning |
|
100% |
5 |
0 |
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100% |
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| pyVHDLModel/Exception.py |
LibraryExistsInDesignError |
|
67% |
3 |
1 |
0 |
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100% |
0 |
0 |
|
67% |
| pyVHDLModel/Exception.py |
LibraryRegisteredToForeignDesignError |
|
67% |
3 |
1 |
0 |
|
100% |
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0 |
|
67% |
| pyVHDLModel/Exception.py |
LibraryNotRegisteredError |
|
67% |
3 |
1 |
0 |
|
100% |
0 |
0 |
|
67% |
| pyVHDLModel/Exception.py |
EntityExistsInLibraryError |
|
100% |
5 |
0 |
0 |
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100% |
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0 |
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100% |
| pyVHDLModel/Exception.py |
ArchitectureExistsInLibraryError |
|
71% |
7 |
2 |
0 |
|
100% |
0 |
0 |
|
71% |
| pyVHDLModel/Exception.py |
PackageExistsInLibraryError |
|
60% |
5 |
2 |
0 |
|
100% |
0 |
0 |
|
60% |
| pyVHDLModel/Exception.py |
PackageBodyExistsError |
|
0% |
5 |
5 |
0 |
|
100% |
0 |
0 |
|
0% |
| pyVHDLModel/Exception.py |
ConfigurationExistsInLibraryError |
|
0% |
5 |
5 |
0 |
|
100% |
0 |
0 |
|
0% |
| pyVHDLModel/Exception.py |
ContextExistsInLibraryError |
|
0% |
5 |
5 |
0 |
|
100% |
0 |
0 |
|
0% |
| pyVHDLModel/Exception.py |
ReferencedLibraryNotExistingError |
|
0% |
5 |
5 |
0 |
|
100% |
0 |
0 |
|
0% |
| pyVHDLModel/Exception.py |
AlreadyInDesignError |
|
100% |
5 |
0 |
0 |
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100% |
0 |
0 |
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100% |
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NotAChildError |
|
100% |
5 |
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100% |
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| pyVHDLModel/Exception.py |
NotInNamespaceError |
|
100% |
8 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateGenericError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicatePortError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateParameterError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateDeclarationError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateAssociationError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
AssociationOrderError |
|
100% |
7 |
0 |
0 |
|
100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateDocumentError |
|
100% |
9 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DuplicateDesignUnitError |
|
100% |
11 |
0 |
0 |
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100% |
0 |
0 |
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100% |
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ElementInUseError |
|
100% |
5 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
LibraryNotFoundError |
|
100% |
3 |
0 |
0 |
|
100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
DesignUnitNotFoundError |
|
100% |
2 |
0 |
0 |
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100% |
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0 |
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100% |
| pyVHDLModel/Exception.py |
EntityNotFoundError |
|
100% |
3 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
PackageNotFoundError |
|
100% |
3 |
0 |
0 |
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100% |
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0 |
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100% |
| pyVHDLModel/Exception.py |
ConfigurationNotFoundError |
|
100% |
3 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
ContextNotFoundError |
|
100% |
3 |
0 |
0 |
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100% |
0 |
0 |
|
100% |
| pyVHDLModel/Exception.py |
VHDLWriterError |
|
100% |
3 |
0 |
0 |
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100% |
0 |
0 |
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100% |
| pyVHDLModel/Exception.py |
LiteralError |
|
100% |
3 |
0 |
0 |
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100% |
0 |
0 |
|
100% |
| pyVHDLModel/Exception.py |
(no class) |
|
100% |
373 |
0 |
7 |
|
100% |
0 |
0 |
|
100% |
| pyVHDLModel/Expression.py |
NullLiteral |
|
100% |
4 |
0 |
0 |
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100% |
0 |
0 |
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