Code Coverage of pyVHDLModel: 73%

Files Functions Classes

coverage.py v7.6.4, created at 2024-11-10 23:46 +0000

File function statements missing excluded branches partial coverage
pyVHDLModel/Association.py AssociationItem.__init__ 5 5 0 2 0 0%
pyVHDLModel/Association.py AssociationItem.Formal 1 1 0 0 0 0%
pyVHDLModel/Association.py AssociationItem.Actual 1 1 0 0 0 0%
pyVHDLModel/Association.py AssociationItem.__str__ 3 3 0 2 0 0%
pyVHDLModel/Association.py (no function) 22 0 0 0 0 100%
pyVHDLModel/Base.py Direction.__str__ 1 0 0 0 0 100%
pyVHDLModel/Base.py Mode.__str__ 1 1 0 0 0 0%
pyVHDLModel/Base.py ModelEntity.__init__ 1 0 0 0 0 100%
pyVHDLModel/Base.py ModelEntity.Parent 1 0 0 0 0 100%
pyVHDLModel/Base.py ModelEntity.GetAncestor 4 4 0 2 0 0%
pyVHDLModel/Base.py NamedEntityMixin.__init__ 2 0 0 0 0 100%
pyVHDLModel/Base.py NamedEntityMixin.Identifier 1 0 0 0 0 100%
pyVHDLModel/Base.py NamedEntityMixin.NormalizedIdentifier 1 0 0 0 0 100%
pyVHDLModel/Base.py MultipleNamedEntityMixin.__init__ 2 0 0 0 0 100%
pyVHDLModel/Base.py MultipleNamedEntityMixin.Identifiers 1 0 0 0 0 100%
pyVHDLModel/Base.py MultipleNamedEntityMixin.NormalizedIdentifiers 1 1 0 0 0 0%
pyVHDLModel/Base.py LabeledEntityMixin.__init__ 2 0 0 0 0 100%
pyVHDLModel/Base.py LabeledEntityMixin.Label 1 1 0 0 0 0%
pyVHDLModel/Base.py LabeledEntityMixin.NormalizedLabel 1 0 0 0 0 100%
pyVHDLModel/Base.py DocumentedEntityMixin.__init__ 1 0 0 0 0 100%
pyVHDLModel/Base.py DocumentedEntityMixin.Documentation 1 0 0 0 0 100%
pyVHDLModel/Base.py ConditionalMixin.__init__ 3 3 0 2 0 0%
pyVHDLModel/Base.py ConditionalMixin.Condition 1 1 0 0 0 0%
pyVHDLModel/Base.py BranchMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Base.py ConditionalBranchMixin.__init__ 2 2 0 0 0 0%
pyVHDLModel/Base.py ReportStatementMixin.__init__ 6 6 0 4 0 0%
pyVHDLModel/Base.py ReportStatementMixin.Message 1 1 0 0 0 0%
pyVHDLModel/Base.py ReportStatementMixin.Severity 1 1 0 0 0 0%
pyVHDLModel/Base.py AssertStatementMixin.__init__ 2 2 0 0 0 0%
pyVHDLModel/Base.py BlockStatementMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Base.py Range.__init__ 6 0 0 0 0 100%
pyVHDLModel/Base.py Range.LeftBound 1 0 0 0 0 100%
pyVHDLModel/Base.py Range.RightBound 1 0 0 0 0 100%
pyVHDLModel/Base.py Range.Direction 1 1 0 0 0 0%
pyVHDLModel/Base.py Range.__str__ 1 0 0 0 0 100%
pyVHDLModel/Base.py WaveformElement.__init__ 6 6 0 2 0 0%
pyVHDLModel/Base.py WaveformElement.Expression 1 1 0 0 0 0%
pyVHDLModel/Base.py WaveformElement.After 1 1 0 0 0 0%
pyVHDLModel/Base.py (no function) 120 0 0 0 0 100%
pyVHDLModel/Common.py Statement.__init__ 2 0 0 0 0 100%
pyVHDLModel/Common.py ProcedureCallMixin.__init__ 7 7 0 4 0 0%
pyVHDLModel/Common.py ProcedureCallMixin.Procedure 1 1 0 0 0 0%
pyVHDLModel/Common.py ProcedureCallMixin.ParameterMappings 1 1 0 0 0 0%
pyVHDLModel/Common.py AssignmentMixin.__init__ 2 2 0 0 0 0%
pyVHDLModel/Common.py AssignmentMixin.Target 1 1 0 0 0 0%
pyVHDLModel/Common.py VariableAssignmentMixin.__init__ 3 3 0 0 0 0%
pyVHDLModel/Common.py VariableAssignmentMixin.Expression 1 1 0 0 0 0%
pyVHDLModel/Common.py (no function) 34 0 0 0 0 100%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin.__init__ 9 0 0 4 0 100%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin.Statements 1 0 0 0 0 100%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin.IterateInstantiations 6 2 0 6 2 67%
pyVHDLModel/Concurrent.py ConcurrentStatementsMixin.IndexStatements 9 6 0 8 1 35%
pyVHDLModel/Concurrent.py Instantiation.__init__ 11 6 0 8 2 37%
pyVHDLModel/Concurrent.py Instantiation.GenericAssociations 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py Instantiation.PortAssociations 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ComponentInstantiation.__init__ 3 3 0 0 0 0%
pyVHDLModel/Concurrent.py ComponentInstantiation.Component 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py EntityInstantiation.__init__ 6 1 0 2 1 75%
pyVHDLModel/Concurrent.py EntityInstantiation.Entity 1 0 0 0 0 100%
pyVHDLModel/Concurrent.py EntityInstantiation.Architecture 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConfigurationInstantiation.__init__ 3 3 0 0 0 0%
pyVHDLModel/Concurrent.py ConfigurationInstantiation.Configuration 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ProcessStatement.__init__ 9 9 0 4 0 0%
pyVHDLModel/Concurrent.py ProcessStatement.SensitivityList 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentProcedureCall.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentBlockStatement.__init__ 11 11 0 4 0 0%
pyVHDLModel/Concurrent.py ConcurrentBlockStatement.PortItems 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateBranch.__init__ 6 6 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateBranch.AlternativeLabel 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateBranch.NormalizedAlternativeLabel 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ElsifGenerateBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ElseGenerateBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.__init__ 12 12 0 6 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.IfBranch 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.ElsifBranches 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.ElseBranch 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.IterateInstantiations 5 5 0 4 0 0%
pyVHDLModel/Concurrent.py IfGenerateStatement.IndexStatement 5 5 0 4 0 0%
pyVHDLModel/Concurrent.py IndexedGenerateChoice.__init__ 3 3 0 0 0 0%
pyVHDLModel/Concurrent.py IndexedGenerateChoice.Expression 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py IndexedGenerateChoice.__str__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py RangedGenerateChoice.__init__ 3 3 0 0 0 0%
pyVHDLModel/Concurrent.py RangedGenerateChoice.Range 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py RangedGenerateChoice.__str__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentCase.__init__ 4 4 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateCase.__init__ 6 6 0 4 0 0%
pyVHDLModel/Concurrent.py GenerateCase.Choices 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py GenerateCase.__str__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py OthersGenerateCase.__str__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement.__init__ 8 8 0 4 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement.SelectExpression 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement.Cases 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement.IterateInstantiations 2 2 0 2 0 0%
pyVHDLModel/Concurrent.py CaseGenerateStatement.IndexStatement 2 2 0 2 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.__init__ 6 6 0 0 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.LoopIndex 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.Range 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.IndexStatement 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.IndexStatements 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ForGenerateStatement.IterateInstantiations 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentSignalAssignment.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentSimpleSignalAssignment.__init__ 6 6 0 4 0 0%
pyVHDLModel/Concurrent.py ConcurrentSimpleSignalAssignment.Waveform 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentSelectedSignalAssignment.__init__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentConditionalSignalAssignment.__init__ 1 1 0 0 0 0%
pyVHDLModel/Concurrent.py ConcurrentAssertStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Concurrent.py (no function) 183 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Reference.__init__ 2 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Reference.Symbols 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py LibraryClause.Symbols 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit.__init__ 23 0 0 10 1 97%
pyVHDLModel/DesignUnit.py DesignUnit.Document 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit.Document 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.Library 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit.Library 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit.ContextItems 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.ContextReferences 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.LibraryReferences 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.PackageReferences 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py DesignUnit.ReferencedLibraries 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.ReferencedPackages 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.ReferencedContexts 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.DependencyVertex 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py DesignUnit.HierarchyVertex 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Context.__init__ 16 3 0 10 1 77%
pyVHDLModel/DesignUnit.py Context.LibraryReferences 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Context.PackageReferences 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Context.ContextReferences 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Context.__str__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py Package.__init__ 11 3 0 4 1 60%
pyVHDLModel/DesignUnit.py Package.PackageBody 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Package.GenericItems 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Package.DeclaredItems 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Package.DeferredConstants 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Package.Components 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Package._IndexOtherDeclaredItem 6 6 0 6 0 0%
pyVHDLModel/DesignUnit.py Package.__str__ 2 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Package.__repr__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py PackageBody.__init__ 5 0 0 0 0 100%
pyVHDLModel/DesignUnit.py PackageBody.Package 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py PackageBody.DeclaredItems 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py PackageBody.LinkDeclaredItemsToPackage 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py PackageBody.__str__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py PackageBody.__repr__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py Entity.__init__ 15 6 0 8 2 48%
pyVHDLModel/DesignUnit.py Entity.GenericItems 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Entity.PortItems 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Entity.Architectures 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Entity.__str__ 3 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Entity.__repr__ 3 3 0 0 0 0%
pyVHDLModel/DesignUnit.py Architecture.__init__ 6 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Architecture.Entity 1 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Architecture.__str__ 3 3 0 0 0 0%
pyVHDLModel/DesignUnit.py Architecture.__repr__ 3 3 0 0 0 0%
pyVHDLModel/DesignUnit.py Component.__init__ 13 13 0 8 0 0%
pyVHDLModel/DesignUnit.py Component.GenericItems 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Component.PortItems 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Component.Entity 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Component.Entity 1 1 0 0 0 0%
pyVHDLModel/DesignUnit.py Configuration.__init__ 2 0 0 0 0 100%
pyVHDLModel/DesignUnit.py Configuration.__str__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py Configuration.__repr__ 2 2 0 0 0 0%
pyVHDLModel/DesignUnit.py (no function) 156 0 0 0 0 100%
pyVHDLModel/Exception.py LibraryExistsInDesignError.__init__ 2 0 0 0 0 100%
pyVHDLModel/Exception.py LibraryExistsInDesignError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py LibraryRegisteredToForeignDesignError.__init__ 2 0 0 0 0 100%
pyVHDLModel/Exception.py LibraryRegisteredToForeignDesignError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py LibraryNotRegisteredError.__init__ 2 2 0 0 0 0%
pyVHDLModel/Exception.py LibraryNotRegisteredError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py EntityExistsInLibraryError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py EntityExistsInLibraryError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py EntityExistsInLibraryError.Entity 1 1 0 0 0 0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError.__init__ 4 4 0 0 0 0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError.Entity 1 1 0 0 0 0%
pyVHDLModel/Exception.py ArchitectureExistsInLibraryError.Architecture 1 1 0 0 0 0%
pyVHDLModel/Exception.py PackageExistsInLibraryError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py PackageExistsInLibraryError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py PackageExistsInLibraryError.Package 1 1 0 0 0 0%
pyVHDLModel/Exception.py PackageBodyExistsError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py PackageBodyExistsError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py PackageBodyExistsError.PackageBody 1 1 0 0 0 0%
pyVHDLModel/Exception.py ConfigurationExistsInLibraryError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py ConfigurationExistsInLibraryError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py ConfigurationExistsInLibraryError.Configuration 1 1 0 0 0 0%
pyVHDLModel/Exception.py ContextExistsInLibraryError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py ContextExistsInLibraryError.Library 1 1 0 0 0 0%
pyVHDLModel/Exception.py ContextExistsInLibraryError.Context 1 1 0 0 0 0%
pyVHDLModel/Exception.py ReferencedLibraryNotExistingError.__init__ 3 3 0 0 0 0%
pyVHDLModel/Exception.py ReferencedLibraryNotExistingError.LibrarySymbol 1 1 0 0 0 0%
pyVHDLModel/Exception.py ReferencedLibraryNotExistingError.Context 1 1 0 0 0 0%
pyVHDLModel/Exception.py (no function) 91 0 2 0 0 100%
pyVHDLModel/Expression.py NullLiteral.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py EnumerationLiteral.__init__ 2 0 0 0 0 100%
pyVHDLModel/Expression.py EnumerationLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py EnumerationLiteral.__str__ 1 0 0 0 0 100%
pyVHDLModel/Expression.py IntegerLiteral.__init__ 2 0 0 0 0 100%
pyVHDLModel/Expression.py IntegerLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py IntegerLiteral.__str__ 1 0 0 0 0 100%
pyVHDLModel/Expression.py FloatingPointLiteral.__init__ 2 0 0 0 0 100%
pyVHDLModel/Expression.py FloatingPointLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py FloatingPointLiteral.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py PhysicalLiteral.__init__ 2 0 0 0 0 100%
pyVHDLModel/Expression.py PhysicalLiteral.UnitName 1 1 0 0 0 0%
pyVHDLModel/Expression.py PhysicalLiteral.__str__ 1 0 0 0 0 100%
pyVHDLModel/Expression.py PhysicalIntegerLiteral.__init__ 2 0 0 0 0 100%
pyVHDLModel/Expression.py PhysicalIntegerLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py PhysicalFloatingLiteral.__init__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py PhysicalFloatingLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py CharacterLiteral.__init__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py CharacterLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py CharacterLiteral.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py StringLiteral.__init__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py StringLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py StringLiteral.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py BitStringLiteral.__init__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py BitStringLiteral.Value 1 1 0 0 0 0%
pyVHDLModel/Expression.py BitStringLiteral.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py ParenthesisExpression.Operand 1 1 0 0 0 0%
pyVHDLModel/Expression.py UnaryExpression.__init__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py UnaryExpression.Operand 1 1 0 0 0 0%
pyVHDLModel/Expression.py UnaryExpression.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py BinaryExpression.__init__ 5 5 0 0 0 0%
pyVHDLModel/Expression.py BinaryExpression.LeftOperand 1 1 0 0 0 0%
pyVHDLModel/Expression.py BinaryExpression.RightOperand 1 1 0 0 0 0%
pyVHDLModel/Expression.py BinaryExpression.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py RangeExpression.Direction 1 1 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpression.__init__ 5 5 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpression.Operand 1 1 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpression.Subtyped 1 1 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpression.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py TernaryExpression.__init__ 1 1 0 0 0 0%
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pyVHDLModel/Expression.py TernaryExpression.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py SubtypeAllocation.__init__ 3 3 0 0 0 0%
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pyVHDLModel/Expression.py SubtypeAllocation.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py QualifiedExpressionAllocation.__init__ 3 3 0 0 0 0%
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pyVHDLModel/Expression.py QualifiedExpressionAllocation.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py AggregateElement.__init__ 3 3 0 0 0 0%
pyVHDLModel/Expression.py AggregateElement.Expression 1 1 0 0 0 0%
pyVHDLModel/Expression.py SimpleAggregateElement.__str__ 1 1 0 0 0 0%
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pyVHDLModel/Expression.py RangedAggregateElement.__init__ 3 3 0 0 0 0%
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pyVHDLModel/Expression.py RangedAggregateElement.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py NamedAggregateElement.__init__ 3 3 0 0 0 0%
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pyVHDLModel/Expression.py NamedAggregateElement.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py OthersAggregateElement.__str__ 1 1 0 0 0 0%
pyVHDLModel/Expression.py Aggregate.__init__ 5 5 0 2 0 0%
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pyVHDLModel/Expression.py Aggregate.__str__ 2 2 0 0 0 0%
pyVHDLModel/Expression.py (no function) 353 0 0 0 0 100%
pyVHDLModel/IEEE.py Ieee.__init__ 1 0 0 0 0 100%
pyVHDLModel/IEEE.py Ieee.LoadSynopsysPackages 1 0 0 0 0 100%
pyVHDLModel/IEEE.py Math_Complex.__init__ 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Math_Complex_Body.__init__ 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Std_logic_1164.__init__ 16 0 0 0 0 100%
pyVHDLModel/IEEE.py std_logic_textio.__init__ 4 0 0 0 0 100%
pyVHDLModel/IEEE.py Std_logic_misc.__init__ 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Bit.__init__ 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Bit_Unsigned_Body.__init__ 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Numeric_Std.__init__ 18 0 0 0 0 100%
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pyVHDLModel/IEEE.py Numeric_Std_Unsigned_Body.__init__ 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg.__init__ 6 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Generic_Pkg_Body.__init__ 3 0 0 0 0 100%
pyVHDLModel/IEEE.py Fixed_Pkg.__init__ 2 0 0 0 0 100%
pyVHDLModel/IEEE.py Float_Generic_Pkg.__init__ 6 0 0 0 0 100%
pyVHDLModel/IEEE.py Float_Pkg.__init__ 2 0 0 0 0 100%
pyVHDLModel/IEEE.py (no function) 75 0 0 0 0 100%
pyVHDLModel/Instantiation.py GenericInstantiationMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py GenericEntityInstantiationMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py SubprogramInstantiationMixin.__init__ 2 2 0 0 0 0%
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pyVHDLModel/Instantiation.py PackageInstantiation.PackageReference 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py PackageInstantiation.GenericAssociations 1 1 0 0 0 0%
pyVHDLModel/Instantiation.py (no function) 33 0 0 0 0 100%
pyVHDLModel/Interface.py InterfaceItemMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Interface.py InterfaceItemWithModeMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Interface.py InterfaceItemWithModeMixin.Mode 1 1 0 0 0 0%
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pyVHDLModel/Interface.py GenericTypeInterfaceItem.__init__ 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericProcedureInterfaceItem.__init__ 2 2 0 0 0 0%
pyVHDLModel/Interface.py GenericFunctionInterfaceItem.__init__ 2 2 0 0 0 0%
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pyVHDLModel/Name.py Name.__init__ 8 0 0 2 0 100%
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pyVHDLModel/Namespace.py Namespace.FindSubtype 16 8 0 10 3 50%
pyVHDLModel/Namespace.py Namespace.FindObject 22 22 0 16 0 0%
pyVHDLModel/Namespace.py (no function) 25 0 0 0 0 100%
pyVHDLModel/Object.py Obj.__init__ 6 0 0 0 0 100%
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pyVHDLModel/Object.py Obj.ObjectVertex 1 1 0 0 0 0%
pyVHDLModel/Object.py WithDefaultExpressionMixin.__init__ 3 1 0 2 1 60%
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pyVHDLModel/Object.py Constant.__init__ 2 0 0 0 0 100%
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pyVHDLModel/Object.py DeferredConstant.__str__ 1 1 0 0 0 0%
pyVHDLModel/Object.py Variable.__init__ 2 2 0 0 0 0%
pyVHDLModel/Object.py Signal.__init__ 2 0 0 0 0 100%
pyVHDLModel/Object.py (no function) 43 0 0 0 0 100%
pyVHDLModel/PSLModel.py VerificationUnit.__init__ 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py VerificationProperty.__init__ 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py VerificationMode.__init__ 1 1 0 0 0 0%
pyVHDLModel/PSLModel.py DefaultClock.__init__ 2 2 0 0 0 0%
pyVHDLModel/PSLModel.py (no function) 21 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedLibrary.__init__ 2 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedLibrary.AddPackages 8 0 0 4 0 100%
pyVHDLModel/Predefined.py PredefinedPackageMixin._AddLibraryClause 4 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedPackageMixin._AddPackageClause 10 1 0 4 1 86%
pyVHDLModel/Predefined.py PredefinedPackage.__init__ 1 0 0 0 0 100%
pyVHDLModel/Predefined.py PredefinedPackageBody.__init__ 2 0 0 0 0 100%
pyVHDLModel/Predefined.py (no function) 21 0 0 0 0 100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.__init__ 13 3 0 4 1 65%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.DeclaredItems 1 0 0 0 0 100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Types 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Subtypes 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Constants 1 0 0 0 0 100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Signals 1 0 0 0 0 100%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.SharedVariables 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Files 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Functions 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.Procedures 1 1 0 0 0 0%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin.IndexDeclaredItems 32 25 0 28 1 20%
pyVHDLModel/Regions.py ConcurrentDeclarationRegionMixin._IndexOtherDeclaredItem 1 1 0 0 0 0%
pyVHDLModel/Regions.py (no function) 38 0 0 0 0 100%
pyVHDLModel/STD.py Std.__init__ 1 0 0 0 0 100%
pyVHDLModel/STD.py Standard.__init__ 54 0 0 0 0 100%
pyVHDLModel/STD.py Env.__init__ 2 0 0 0 0 100%
pyVHDLModel/STD.py (no function) 25 0 0 0 0 100%
pyVHDLModel/Sequential.py SequentialStatementsMixin.__init__ 5 5 0 4 0 0%
pyVHDLModel/Sequential.py SequentialStatementsMixin.Statements 1 1 0 0 0 0%
pyVHDLModel/Sequential.py SequentialProcedureCall.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialSignalAssignment.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialSimpleSignalAssignment.__init__ 6 6 0 4 0 0%
pyVHDLModel/Sequential.py SequentialSimpleSignalAssignment.Waveform 1 1 0 0 0 0%
pyVHDLModel/Sequential.py SequentialVariableAssignment.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialReportStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialAssertStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py Branch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py IfBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ElsifBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ElseBranch.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py IfStatement.__init__ 12 12 0 6 0 0%
pyVHDLModel/Sequential.py IfStatement.IfBranch 1 1 0 0 0 0%
pyVHDLModel/Sequential.py IfStatement.ElsIfBranches 1 1 0 0 0 0%
pyVHDLModel/Sequential.py IfStatement.ElseBranch 1 1 0 0 0 0%
pyVHDLModel/Sequential.py IndexedChoice.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py IndexedChoice.Expression 1 1 0 0 0 0%
pyVHDLModel/Sequential.py IndexedChoice.__str__ 1 1 0 0 0 0%
pyVHDLModel/Sequential.py RangedChoice.__init__ 3 3 0 0 0 0%
pyVHDLModel/Sequential.py RangedChoice.Range 1 1 0 0 0 0%
pyVHDLModel/Sequential.py RangedChoice.__str__ 1 1 0 0 0 0%
pyVHDLModel/Sequential.py SequentialCase.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py SequentialCase.Choices 1 1 0 0 0 0%
pyVHDLModel/Sequential.py Case.__init__ 6 6 0 4 0 0%
pyVHDLModel/Sequential.py Case.Choices 1 1 0 0 0 0%
pyVHDLModel/Sequential.py Case.__str__ 1 1 0 0 0 0%
pyVHDLModel/Sequential.py OthersCase.__str__ 1 1 0 0 0 0%
pyVHDLModel/Sequential.py CaseStatement.__init__ 8 8 0 4 0 0%
pyVHDLModel/Sequential.py CaseStatement.SelectExpression 1 1 0 0 0 0%
pyVHDLModel/Sequential.py CaseStatement.Cases 1 1 0 0 0 0%
pyVHDLModel/Sequential.py LoopStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ForLoopStatement.__init__ 4 4 0 0 0 0%
pyVHDLModel/Sequential.py ForLoopStatement.LoopIndex 1 1 0 0 0 0%
pyVHDLModel/Sequential.py ForLoopStatement.Range 1 1 0 0 0 0%
pyVHDLModel/Sequential.py WhileLoopStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py LoopControlStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py LoopControlStatement.LoopReference 1 1 0 0 0 0%
pyVHDLModel/Sequential.py ReturnStatement.__init__ 2 2 0 0 0 0%
pyVHDLModel/Sequential.py ReturnStatement.ReturnValue 1 1 0 0 0 0%
pyVHDLModel/Sequential.py WaitStatement.__init__ 11 11 0 6 0 0%
pyVHDLModel/Sequential.py WaitStatement.SensitivityList 1 1 0 0 0 0%
pyVHDLModel/Sequential.py WaitStatement.Timeout 1 1 0 0 0 0%
pyVHDLModel/Sequential.py SequentialDeclarationsMixin.__init__ 5 5 0 4 0 0%
pyVHDLModel/Sequential.py SequentialDeclarationsMixin.DeclaredItems 1 1 0 0 0 0%
pyVHDLModel/Sequential.py (no function) 158 0 0 0 0 100%
pyVHDLModel/Subprogram.py Subprogram.__init__ 8 8 0 0 0 0%
pyVHDLModel/Subprogram.py Subprogram.GenericItems 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Subprogram.ParameterItems 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Subprogram.DeclaredItems 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Subprogram.Statements 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Subprogram.IsPure 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Procedure.__init__ 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Function.__init__ 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py Function.ReturnType 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py MethodMixin.__init__ 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py MethodMixin.ProtectedType 1 1 0 0 0 0%
pyVHDLModel/Subprogram.py ProcedureMethod.__init__ 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py FunctionMethod.__init__ 2 2 0 0 0 0%
pyVHDLModel/Subprogram.py (no function) 45 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol.__init__ 3 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol.Name 1 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol.Reference 1 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol.IsResolved 1 0 0 0 0 100%
pyVHDLModel/Symbol.py Symbol.__bool__ 1 1 0 0 0 0%
pyVHDLModel/Symbol.py Symbol.__repr__ 3 0 0 2 0 100%
pyVHDLModel/Symbol.py Symbol.__str__ 3 0 0 2 0 100%
pyVHDLModel/Symbol.py LibraryReferenceSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py LibraryReferenceSymbol.Library 1 0 0 0 0 100%
pyVHDLModel/Symbol.py LibraryReferenceSymbol.Library 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageReferenceSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageReferenceSymbol.Package 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageReferenceSymbol.Package 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ContextReferenceSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ContextReferenceSymbol.Context 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ContextReferenceSymbol.Context 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageMemberReferenceSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageMemberReferenceSymbol.Member 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageMemberReferenceSymbol.Member 1 0 0 0 0 100%
pyVHDLModel/Symbol.py AllPackageMembersReferenceSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py AllPackageMembersReferenceSymbol.Members 1 0 0 0 0 100%
pyVHDLModel/Symbol.py AllPackageMembersReferenceSymbol.Members 1 0 0 0 0 100%
pyVHDLModel/Symbol.py EntityInstantiationSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py EntityInstantiationSymbol.Entity 1 0 0 0 0 100%
pyVHDLModel/Symbol.py EntityInstantiationSymbol.Entity 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ComponentInstantiationSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ComponentInstantiationSymbol.Component 1 1 0 0 0 0%
pyVHDLModel/Symbol.py ComponentInstantiationSymbol.Component 1 1 0 0 0 0%
pyVHDLModel/Symbol.py ConfigurationInstantiationSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ConfigurationInstantiationSymbol.Configuration 1 1 0 0 0 0%
pyVHDLModel/Symbol.py ConfigurationInstantiationSymbol.Configuration 1 1 0 0 0 0%
pyVHDLModel/Symbol.py EntitySymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py EntitySymbol.Entity 1 0 0 0 0 100%
pyVHDLModel/Symbol.py EntitySymbol.Entity 1 0 0 0 0 100%
pyVHDLModel/Symbol.py ArchitectureSymbol.__init__ 1 1 0 0 0 0%
pyVHDLModel/Symbol.py ArchitectureSymbol.Architecture 1 1 0 0 0 0%
pyVHDLModel/Symbol.py ArchitectureSymbol.Architecture 1 1 0 0 0 0%
pyVHDLModel/Symbol.py PackageSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageSymbol.Package 1 0 0 0 0 100%
pyVHDLModel/Symbol.py PackageSymbol.Package 1 0 0 0 0 100%
pyVHDLModel/Symbol.py RecordElementSymbol.__init__ 1 1 0 0 0 0%
pyVHDLModel/Symbol.py SubtypeSymbol.__init__ 1 0 0 0 0 100%
pyVHDLModel/Symbol.py SubtypeSymbol.Subtype 1 1 0 0 0 0%
pyVHDLModel/Symbol.py SubtypeSymbol.Subtype 1 1 0 0 0 0%
pyVHDLModel/Symbol.py SimpleObjectOrFunctionCallSymbol.__init__ 1 1 0 0 0 0%
pyVHDLModel/Symbol.py IndexedObjectOrFunctionCallSymbol.__init__ 1 1 0 0 0 0%
pyVHDLModel/Symbol.py (no function) 168 0 0 0 0 100%
pyVHDLModel/Type.py BaseType.__init__ 4 0 0 0 0 100%
pyVHDLModel/Type.py Subtype.__init__ 5 0 0 0 0 100%
pyVHDLModel/Type.py Subtype.Type 1 1 0 0 0 0%
pyVHDLModel/Type.py Subtype.BaseType 1 1 0 0 0 0%
pyVHDLModel/Type.py Subtype.Range 1 1 0 0 0 0%
pyVHDLModel/Type.py Subtype.ResolutionFunction 1 1 0 0 0 0%
pyVHDLModel/Type.py Subtype.__str__ 1 0 0 0 0 100%
pyVHDLModel/Type.py RangedScalarType.__init__ 2 0 0 0 0 100%
pyVHDLModel/Type.py RangedScalarType.Range 1 0 0 0 0 100%
pyVHDLModel/Type.py NumericTypeMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Type.py DiscreteTypeMixin.__init__ 1 1 0 0 0 0%
pyVHDLModel/Type.py EnumeratedType.__init__ 6 0 0 4 1 90%
pyVHDLModel/Type.py EnumeratedType.Literals 1 1 0 0 0 0%
pyVHDLModel/Type.py EnumeratedType.__str__ 1 0 0 0 0 100%
pyVHDLModel/Type.py IntegerType.__init__ 1 0 0 0 0 100%
pyVHDLModel/Type.py IntegerType.__str__ 1 0 0 0 0 100%
pyVHDLModel/Type.py RealType.__init__ 1 0 0 0 0 100%
pyVHDLModel/Type.py RealType.__str__ 1 1 0 0 0 0%
pyVHDLModel/Type.py PhysicalType.__init__ 6 0 0 2 0 100%
pyVHDLModel/Type.py PhysicalType.PrimaryUnit 1 1 0 0 0 0%
pyVHDLModel/Type.py PhysicalType.SecondaryUnits 1 1 0 0 0 0%
pyVHDLModel/Type.py PhysicalType.__str__ 1 0 0 0 0 100%
pyVHDLModel/Type.py ArrayType.__init__ 5 0 0 2 0 100%
pyVHDLModel/Type.py ArrayType.Dimensions 1 1 0 0 0 0%
pyVHDLModel/Type.py ArrayType.ElementType 1 1 0 0 0 0%
pyVHDLModel/Type.py ArrayType.__str__ 1 0 0 0 0 100%
pyVHDLModel/Type.py RecordTypeElement.__init__ 4 4 0 0 0 0%
pyVHDLModel/Type.py RecordTypeElement.Subtype 1 1 0 0 0 0%
pyVHDLModel/Type.py RecordTypeElement.__str__ 1 1 0 0 0 0%
pyVHDLModel/Type.py RecordType.__init__ 6 2 0 4 2 60%
pyVHDLModel/Type.py RecordType.Elements 1 1 0 0 0 0%
pyVHDLModel/Type.py RecordType.__str__ 1 1 0 0 0 0%
pyVHDLModel/Type.py ProtectedType.__init__ 6 6 0 4 0 0%
pyVHDLModel/Type.py ProtectedType.Methods 1 1 0 0 0 0%
pyVHDLModel/Type.py ProtectedTypeBody.__init__ 6 6 0 4 0 0%
pyVHDLModel/Type.py ProtectedTypeBody.Methods 1 1 0 0 0 0%
pyVHDLModel/Type.py AccessType.__init__ 3 3 0 0 0 0%
pyVHDLModel/Type.py AccessType.DesignatedSubtype 1 1 0 0 0 0%
pyVHDLModel/Type.py AccessType.__str__ 1 1 0 0 0 0%
pyVHDLModel/Type.py FileType.__init__ 3 3 0 0 0 0%
pyVHDLModel/Type.py FileType.DesignatedSubtype 1 1 0 0 0 0%
pyVHDLModel/Type.py FileType.__str__ 1 1 0 0 0 0%
pyVHDLModel/Type.py (no function) 130 0 0 0 0 100%
pyVHDLModel/__init__.py VHDLVersion.__init__ 3 0 0 4 0 100%
pyVHDLModel/__init__.py VHDLVersion.Parse 4 4 0 0 0 0%
pyVHDLModel/__init__.py VHDLVersion.__lt__ 3 3 0 2 0 0%
pyVHDLModel/__init__.py VHDLVersion.__le__ 3 3 0 2 0 0%
pyVHDLModel/__init__.py VHDLVersion.__gt__ 3 3 0 2 0 0%
pyVHDLModel/__init__.py VHDLVersion.__ge__ 3 3 0 2 0 0%
pyVHDLModel/__init__.py VHDLVersion.__ne__ 3 3 0 2 0 0%
pyVHDLModel/__init__.py VHDLVersion.__eq__ 5 5 0 4 0 0%
pyVHDLModel/__init__.py VHDLVersion.IsVHDL 1 1 0 0 0 0%
pyVHDLModel/__init__.py VHDLVersion.IsAMS 1 1 0 0 0 0%
pyVHDLModel/__init__.py VHDLVersion.__str__ 8 8 0 6 0 0%
pyVHDLModel/__init__.py VHDLVersion.__repr__ 5 5 0 4 0 0%
pyVHDLModel/__init__.py ObjectClass.__str__ 1 1 0 0 0 0%
pyVHDLModel/__init__.py Design.__init__ 9 0 0 0 0 100%
pyVHDLModel/__init__.py Design.Libraries 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.Documents 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.CompileOrderGraph 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.DependencyGraph 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.HierarchyGraph 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.ObjectGraph 1 1 0 0 0 0%
pyVHDLModel/__init__.py Design.TopLevel 11 11 0 6 0 0%
pyVHDLModel/__init__.py Design.LoadStdLibrary 7 0 0 2 0 100%
pyVHDLModel/__init__.py Design.LoadIEEELibrary 7 0 0 2 0 100%
pyVHDLModel/__init__.py Design.AddLibrary 7 0 0 4 0 100%
pyVHDLModel/__init__.py Design.GetLibrary 8 0 0 0 0 100%
pyVHDLModel/__init__.py Design.AddDocument 42 11 0 30 6 71%
pyVHDLModel/__init__.py Design.IterateDesignUnits 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.Analyze 2 0 0 0 0 100%
pyVHDLModel/__init__.py Design.AnalyzeDependencies 14 0 0 0 0 100%
pyVHDLModel/__init__.py Design.AnalyzeObjects 4 0 0 0 0 100%
pyVHDLModel/__init__.py Design.CreateDependencyGraph 37 0 0 16 0 100%
pyVHDLModel/__init__.py Design.CreateCompileOrderGraph 9 0 0 4 0 100%
pyVHDLModel/__init__.py Design.ImportObjects 7 0 0 8 0 100%
pyVHDLModel/__init__.py Design.ImportObjects._ImportObjects 9 3 0 12 2 67%
pyVHDLModel/__init__.py Design.CreateTypeAndObjectGraph 11 0 0 8 0 100%
pyVHDLModel/__init__.py Design.CreateTypeAndObjectGraph._HandlePackage 36 20 0 14 5 50%
pyVHDLModel/__init__.py Design.CreateTypeAndObjectGraph._LinkSymbolsInExpression 13 8 0 8 4 43%
pyVHDLModel/__init__.py Design.CreateTypeAndObjectGraph._LinkItems 32 8 0 20 4 73%
pyVHDLModel/__init__.py Design.LinkContexts 43 9 1 16 3 80%
pyVHDLModel/__init__.py Design.LinkArchitectures 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.LinkPackageBodies 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.LinkLibraryReferences 40 5 0 16 1 89%
pyVHDLModel/__init__.py Design.LinkPackageReferences 46 10 1 30 5 80%
pyVHDLModel/__init__.py Design.LinkContextReferences 33 6 0 24 2 82%
pyVHDLModel/__init__.py Design.LinkComponents 8 5 0 4 1 50%
pyVHDLModel/__init__.py Design.LinkInstantiations 37 20 0 16 2 47%
pyVHDLModel/__init__.py Design.IndexPackages 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.IndexPackageBodies 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.IndexEntities 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.IndexArchitectures 2 0 0 2 0 100%
pyVHDLModel/__init__.py Design.CreateHierarchyGraph 17 0 0 12 0 100%
pyVHDLModel/__init__.py Design.ComputeCompileOrder 14 6 0 6 1 55%
pyVHDLModel/__init__.py Design.ComputeCompileOrder.predicate 1 0 0 0 0 100%
pyVHDLModel/__init__.py Design.IterateDocumentsInCompileOrder 4 1 0 4 1 75%
pyVHDLModel/__init__.py Design.__repr__ 1 1 0 0 0 0%
pyVHDLModel/__init__.py Library.__init__ 9 0 0 0 0 100%
pyVHDLModel/__init__.py Library.Contexts 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.Configurations 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.Entities 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.Architectures 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.Packages 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.PackageBodies 1 0 0 0 0 100%
pyVHDLModel/__init__.py Library.DependencyVertex 1 1 0 0 0 0%
pyVHDLModel/__init__.py Library.IterateDesignUnits 19 0 0 26 0 100%
pyVHDLModel/__init__.py Library.LinkArchitectures 13 3 0 8 2 76%
pyVHDLModel/__init__.py Library.LinkPackageBodies 9 1 0 4 1 85%
pyVHDLModel/__init__.py Library.IndexPackages 3 0 0 4 1 86%
pyVHDLModel/__init__.py Library.IndexPackageBodies 2 0 0 2 0 100%
pyVHDLModel/__init__.py Library.IndexEntities 2 0 0 2 0 100%
pyVHDLModel/__init__.py Library.IndexArchitectures 4 0 0 4 0 100%
pyVHDLModel/__init__.py Library.__repr__ 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.__init__ 15 0 0 0 0 100%
pyVHDLModel/__init__.py Document._AddEntity 9 3 2 4 2 62%
pyVHDLModel/__init__.py Document._AddArchitecture 14 5 2 4 1 56%
pyVHDLModel/__init__.py Document._AddPackage 9 3 2 4 2 62%
pyVHDLModel/__init__.py Document._AddPackageBody 9 3 2 4 2 62%
pyVHDLModel/__init__.py Document._AddContext 9 3 2 4 2 62%
pyVHDLModel/__init__.py Document._AddConfiguration 9 3 2 4 2 62%
pyVHDLModel/__init__.py Document._AddVerificationUnit 9 9 2 4 0 0%
pyVHDLModel/__init__.py Document._AddVerificationProperty 9 9 2 4 0 0%
pyVHDLModel/__init__.py Document._AddVerificationMode 9 9 2 4 0 0%
pyVHDLModel/__init__.py Document._AddDesignUnit 23 10 4 20 2 58%
pyVHDLModel/__init__.py Document.Path 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.DesignUnits 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.Contexts 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.Configurations 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.Entities 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.Architectures 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.Packages 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.PackageBodies 1 0 0 0 0 100%
pyVHDLModel/__init__.py Document.VerificationUnits 1 1 0 0 0 0%
pyVHDLModel/__init__.py Document.VerificationProperties 1 1 0 0 0 0%
pyVHDLModel/__init__.py Document.VerificationModes 1 1 0 0 0 0%
pyVHDLModel/__init__.py Document.CompileOrderVertex 1 1 0 0 0 0%
pyVHDLModel/__init__.py Document.IterateDesignUnits 19 0 0 26 1 98%
pyVHDLModel/__init__.py Document.__repr__ 1 1 0 0 0 0%
pyVHDLModel/__init__.py (no function) 278 0 0 0 0 100%
Total   4149 992 33 702 76 73%

No items found using the specified filter.

4 empty functions skipped.