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pyVHDLModel/__init__.py |
Design.__init__ |
9 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.Libraries |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.Documents |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.CompileOrderGraph |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.DependencyGraph |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.HierarchyGraph |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.ObjectGraph |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
Design.TopLevel |
11 |
11 |
0 |
6 |
0 |
0% |
pyVHDLModel/__init__.py |
Design.LoadStdLibrary |
7 |
0 |
0 |
2 |
0 |
100% |
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Design.LoadIEEELibrary |
7 |
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0 |
2 |
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Design.AddLibrary |
7 |
0 |
0 |
4 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.GetLibrary |
8 |
0 |
0 |
0 |
0 |
100% |
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Design.AddDocument |
42 |
11 |
0 |
30 |
6 |
71% |
pyVHDLModel/__init__.py |
Design.IterateDesignUnits |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.Analyze |
2 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.AnalyzeDependencies |
14 |
0 |
0 |
0 |
0 |
100% |
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Design.AnalyzeObjects |
4 |
0 |
0 |
0 |
0 |
100% |
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Design.CreateDependencyGraph |
37 |
0 |
0 |
16 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.CreateCompileOrderGraph |
9 |
0 |
0 |
4 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.ImportObjects |
7 |
0 |
0 |
8 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.ImportObjects._ImportObjects |
9 |
3 |
0 |
12 |
2 |
67% |
pyVHDLModel/__init__.py |
Design.CreateTypeAndObjectGraph |
11 |
0 |
0 |
8 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.CreateTypeAndObjectGraph._HandlePackage |
36 |
20 |
0 |
14 |
5 |
50% |
pyVHDLModel/__init__.py |
Design.CreateTypeAndObjectGraph._LinkSymbolsInExpression |
13 |
8 |
0 |
8 |
4 |
43% |
pyVHDLModel/__init__.py |
Design.CreateTypeAndObjectGraph._LinkItems |
32 |
8 |
0 |
20 |
4 |
73% |
pyVHDLModel/__init__.py |
Design.LinkContexts |
43 |
9 |
1 |
16 |
3 |
80% |
pyVHDLModel/__init__.py |
Design.LinkArchitectures |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.LinkPackageBodies |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.LinkLibraryReferences |
40 |
5 |
0 |
16 |
1 |
89% |
pyVHDLModel/__init__.py |
Design.LinkPackageReferences |
46 |
10 |
1 |
30 |
5 |
80% |
pyVHDLModel/__init__.py |
Design.LinkContextReferences |
33 |
6 |
0 |
24 |
2 |
82% |
pyVHDLModel/__init__.py |
Design.LinkComponents |
8 |
5 |
0 |
4 |
1 |
50% |
pyVHDLModel/__init__.py |
Design.LinkInstantiations |
37 |
20 |
0 |
16 |
2 |
47% |
pyVHDLModel/__init__.py |
Design.IndexPackages |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.IndexPackageBodies |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.IndexEntities |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.IndexArchitectures |
2 |
0 |
0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.CreateHierarchyGraph |
17 |
0 |
0 |
12 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.ComputeCompileOrder |
14 |
6 |
0 |
6 |
1 |
55% |
pyVHDLModel/__init__.py |
Design.ComputeCompileOrder.predicate |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Design.IterateDocumentsInCompileOrder |
4 |
1 |
0 |
4 |
1 |
75% |
pyVHDLModel/__init__.py |
Design.__repr__ |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
Library.__init__ |
9 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Library.Contexts |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Library.Configurations |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Library.Entities |
1 |
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0 |
0 |
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100% |
pyVHDLModel/__init__.py |
Library.Architectures |
1 |
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0 |
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100% |
pyVHDLModel/__init__.py |
Library.Packages |
1 |
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0 |
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pyVHDLModel/__init__.py |
Library.PackageBodies |
1 |
0 |
0 |
0 |
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100% |
pyVHDLModel/__init__.py |
Library.DependencyVertex |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
Library.IterateDesignUnits |
19 |
0 |
0 |
26 |
0 |
100% |
pyVHDLModel/__init__.py |
Library.LinkArchitectures |
13 |
3 |
0 |
8 |
2 |
76% |
pyVHDLModel/__init__.py |
Library.LinkPackageBodies |
9 |
1 |
0 |
4 |
1 |
85% |
pyVHDLModel/__init__.py |
Library.IndexPackages |
3 |
0 |
0 |
4 |
1 |
86% |
pyVHDLModel/__init__.py |
Library.IndexPackageBodies |
2 |
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0 |
2 |
0 |
100% |
pyVHDLModel/__init__.py |
Library.IndexEntities |
2 |
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0 |
2 |
0 |
100% |
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4 |
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4 |
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Library.__repr__ |
1 |
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pyVHDLModel/__init__.py |
Document.__init__ |
15 |
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0 |
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100% |
pyVHDLModel/__init__.py |
Document._AddEntity |
9 |
3 |
2 |
4 |
2 |
62% |
pyVHDLModel/__init__.py |
Document._AddArchitecture |
14 |
5 |
2 |
4 |
1 |
56% |
pyVHDLModel/__init__.py |
Document._AddPackage |
9 |
3 |
2 |
4 |
2 |
62% |
pyVHDLModel/__init__.py |
Document._AddPackageBody |
9 |
3 |
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4 |
2 |
62% |
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Document._AddContext |
9 |
3 |
2 |
4 |
2 |
62% |
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Document._AddConfiguration |
9 |
3 |
2 |
4 |
2 |
62% |
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Document._AddVerificationUnit |
9 |
9 |
2 |
4 |
0 |
0% |
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Document._AddVerificationProperty |
9 |
9 |
2 |
4 |
0 |
0% |
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Document._AddVerificationMode |
9 |
9 |
2 |
4 |
0 |
0% |
pyVHDLModel/__init__.py |
Document._AddDesignUnit |
23 |
10 |
4 |
20 |
2 |
58% |
pyVHDLModel/__init__.py |
Document.Path |
1 |
0 |
0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Document.DesignUnits |
1 |
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0 |
0 |
0 |
100% |
pyVHDLModel/__init__.py |
Document.Contexts |
1 |
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0 |
0 |
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100% |
pyVHDLModel/__init__.py |
Document.Configurations |
1 |
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0 |
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pyVHDLModel/__init__.py |
Document.Entities |
1 |
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0 |
0 |
100% |
pyVHDLModel/__init__.py |
Document.Architectures |
1 |
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0 |
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Document.Packages |
1 |
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Document.PackageBodies |
1 |
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pyVHDLModel/__init__.py |
Document.VerificationUnits |
1 |
1 |
0 |
0 |
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0% |
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Document.VerificationProperties |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
Document.VerificationModes |
1 |
1 |
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0 |
0 |
0% |
pyVHDLModel/__init__.py |
Document.CompileOrderVertex |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
Document.IterateDesignUnits |
19 |
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0 |
26 |
1 |
98% |
pyVHDLModel/__init__.py |
Document.__repr__ |
1 |
1 |
0 |
0 |
0 |
0% |
pyVHDLModel/__init__.py |
(no function) |
278 |
0 |
0 |
0 |
0 |
100% |