Statements					Branches				Total
File	function		coverage	statements	missing	excluded		coverage	branches	partial		coverage
pyVHDLModel/Association.py	AssociationItem.__init__		100%	7	0	0		100%	4	0		100%
pyVHDLModel/Association.py	AssociationItem.Formal		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	AssociationItem.Actual		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	AssociationItem.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Association.py	AssociationItem.Visit		100%	7	0	0		75%	4	1		91%
pyVHDLModel/Association.py	AssociationItem.__str__		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin.__init__		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin.GenericAssociationItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin._VisitGenericMapAspect		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin.AddGenericAssociationItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin.InsertGenericAssociationItem		100%	43	0	0		100%	28	0		100%
pyVHDLModel/Association.py	GenericMapAspectMixin.RemoveGenericAssociationItem		100%	12	0	0		88%	8	1		95%
pyVHDLModel/Association.py	PortMapAspectMixin.__init__		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Association.py	PortMapAspectMixin.PortAssociationItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	PortMapAspectMixin._VisitPortMapAspect		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Association.py	PortMapAspectMixin.AddPortAssociationItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Association.py	PortMapAspectMixin.InsertPortAssociationItem		84%	43	7	0		86%	28	4		85%
pyVHDLModel/Association.py	PortMapAspectMixin.RemovePortAssociationItem		67%	12	4	0		62%	8	3		65%
pyVHDLModel/Association.py	(no function)		98%	52	1	0		50%	2	1		96%
pyVHDLModel/Base.py	Direction.ReservedWord		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	Direction.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	Mode.ReservedWord		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	Mode.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ModelEntity.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ModelEntity.Parent		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ModelEntity.Parent		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Base.py	ModelEntity.GetAncestor		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Base.py	NamedEntityMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	NamedEntityMixin.Identifier		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	NamedEntityMixin.NormalizedIdentifier		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	OptionallyNamedEntityMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	OptionallyNamedEntityMixin.Identifier		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	OptionallyNamedEntityMixin.NormalizedIdentifier		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	MultipleNamedEntityMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	MultipleNamedEntityMixin.Identifiers		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	MultipleNamedEntityMixin.NormalizedIdentifiers		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	identifiersOf		57%	7	3	0		75%	4	1		64%
pyVHDLModel/Base.py	normalizedIdentifiersOf		57%	7	3	0		75%	4	1		64%
pyVHDLModel/Base.py	normalizedDeclaredNamesOf		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Base.py	LabeledEntityMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	LabeledEntityMixin.Label		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	LabeledEntityMixin.NormalizedLabel		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	DocumentedEntityMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	DocumentedEntityMixin.Documentation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ConditionalMixin.__init__		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Base.py	ConditionalMixin.Condition		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	BranchMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ConditionalBranchMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ReportStatementMixin.__init__		100%	6	0	0		100%	4	0		100%
pyVHDLModel/Base.py	ReportStatementMixin._VisitReportAndSeverity		100%	6	0	0		100%	4	0		100%
pyVHDLModel/Base.py	ReportStatementMixin.Message		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ReportStatementMixin.Severity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	AssertStatementMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	AssertStatementMixin._VisitAssertion		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Base.py	BlockStatementMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	ChoicesMixin.__init__		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Base.py	ChoicesMixin.Choices		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.__init__		100%	6	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.LeftBound		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.RightBound		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.Direction		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Base.py	SimpleRange.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	RangeFromName.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Base.py	RangeFromName.Symbol		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	RangeFromName.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	RangeFromName.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Base.py	RangeFromName.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	WaveformElement.__init__		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Base.py	WaveformElement.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Base.py	WaveformElement.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	WaveformElement.After		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Base.py	(no function)		99%	297	2	0		50%	2	1		99%
pyVHDLModel/Common.py	AllowBlackboxMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	AllowBlackboxMixin.AllowBlackbox		100%	6	0	0		100%	4	0		100%
pyVHDLModel/Common.py	AllowBlackboxMixin.AllowBlackbox		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	Statement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin.__init__		100%	7	0	0		100%	4	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin._VisitProcedureCall		100%	9	0	0		100%	6	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin.Procedure		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin.ParameterAssociationItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin.AddParameterAssociationItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ProcedureCallMixin.InsertParameterAssociationItem		84%	43	7	0		86%	28	4		85%
pyVHDLModel/Common.py	ProcedureCallMixin.RemoveParameterAssociationItem		100%	12	0	0		88%	8	1		95%
pyVHDLModel/Common.py	AssignmentMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Common.py	AssignmentMixin.Target		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SignalAssignmentMixin.Target		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	VariableAssignmentMixin.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Common.py	VariableAssignmentMixin.Target		0%	1	1	0		100%	0	0		0%
pyVHDLModel/Common.py	VariableAssignmentMixin.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	WaveformMixin.__init__		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Common.py	WaveformMixin._VisitWaveform		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Common.py	WaveformMixin.Waveform		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ExpressionMixin.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ExpressionMixin.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ConditionalWaveform.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ConditionalWaveform.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Common.py	ConditionalExpression.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Common.py	ConditionalExpression.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Common.py	ConditionalWaveformsMixin.__init__		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Common.py	ConditionalWaveformsMixin._VisitConditionalWaveforms		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Common.py	ConditionalWaveformsMixin.ConditionalWaveforms		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedWaveform.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedWaveform.Visit		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Common.py	OthersSelectedWaveform.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Common.py	OthersSelectedWaveform.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedExpression.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedExpression.Visit		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Common.py	OthersSelectedExpression.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Common.py	OthersSelectedExpression.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedWaveformsMixin.__init__		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Common.py	SelectedWaveformsMixin._VisitSelectedWaveforms		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Common.py	SelectedWaveformsMixin.SelectedWaveforms		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	SelectedExpressionsMixin.__init__		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Common.py	SelectedExpressionsMixin._VisitSelectedExpressions		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Common.py	SelectedExpressionsMixin.SelectedExpressions		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Common.py	(no function)		99%	115	1	0		50%	2	1		98%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.__init__		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.Statements		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin._VisitStatements		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin._Labels		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.IterateInstantiations		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.IndexStatements		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin._IndexStatement		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin._UnindexStatement		100%	4	0	0		75%	4	1		88%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.AddStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.InsertStatement		100%	29	0	0		100%	16	0		100%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.InsertStatementBefore		71%	14	4	0		70%	10	3		71%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.InsertStatementAfter		64%	14	5	0		60%	10	4		62%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.RemoveStatement		100%	17	0	0		83%	12	2		93%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.MoveStatement		69%	26	8	0		69%	16	5		69%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.MoveStatementBefore		67%	15	5	0		70%	10	3		68%
pyVHDLModel/Concurrent.py	ConcurrentStatementsMixin.MoveStatementAfter		47%	15	8	0		40%	10	4		44%
pyVHDLModel/Concurrent.py	Instantiation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	Instantiation._VisitMapAspects		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ComponentInstantiation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ComponentInstantiation.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ComponentInstantiation.Component		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	EntityInstantiation.__init__		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	EntityInstantiation.Visit		100%	8	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	EntityInstantiation.Entity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	EntityInstantiation.Architecture		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConfigurationInstantiation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConfigurationInstantiation.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConfigurationInstantiation.Configuration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ProcessStatement.__init__		100%	9	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	ProcessStatement.Visit		100%	13	0	0		100%	6	0		100%
pyVHDLModel/Concurrent.py	ProcessStatement.Parent		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ProcessStatement._LabelRegion		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ProcessStatement.SensitivityList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentProcedureCall.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentProcedureCall.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentBlockStatement.__init__		92%	13	1	0		50%	2	1		87%
pyVHDLModel/Concurrent.py	ConcurrentBlockStatement.Visit		100%	9	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentBlockStatement.Parent		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentBlockStatement.IndexDeclaredItems		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentBlockStatement._Declarations		0%	1	1	0		100%	0	0		0%
pyVHDLModel/Concurrent.py	GenerateBranch.__init__		88%	8	1	0		50%	2	1		80%
pyVHDLModel/Concurrent.py	GenerateBranch.AlternativeLabel		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	GenerateBranch.NormalizedAlternativeLabel		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateBranch.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ElsifGenerateBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ElsifGenerateBranch.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ElseGenerateBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ElseGenerateBranch.Visit		100%	6	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	GenerateStatement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.__init__		100%	12	0	0		100%	6	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.Visit		100%	7	0	0		75%	4	1		91%
pyVHDLModel/Concurrent.py	IfGenerateStatement.Parent		100%	9	0	0		67%	6	2		87%
pyVHDLModel/Concurrent.py	IfGenerateStatement.IfBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.ElsifBranches		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.ElseBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.IterateInstantiations		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	IfGenerateStatement.IndexStatement		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	IndexedGenerateChoice.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IndexedGenerateChoice.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IndexedGenerateChoice.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	IndexedGenerateChoice.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	RangedGenerateChoice.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	RangedGenerateChoice.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	RangedGenerateChoice.Range		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	RangedGenerateChoice.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ConcurrentCase.__init__		88%	8	1	0		50%	2	1		80%
pyVHDLModel/Concurrent.py	GenerateCase.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	GenerateCase.Visit		100%	10	0	0		100%	4	0		100%
pyVHDLModel/Concurrent.py	GenerateCase.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	OthersGenerateCase.Visit		100%	6	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	OthersGenerateCase.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.__init__		100%	8	0	0		75%	4	1		92%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.Parent		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.SelectExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.Cases		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.IterateInstantiations		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	CaseGenerateStatement.IndexStatement		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Concurrent.py	ForGenerateStatement.__init__		88%	8	1	0		50%	2	1		80%
pyVHDLModel/Concurrent.py	ForGenerateStatement.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ForGenerateStatement.Parent		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Concurrent.py	ForGenerateStatement.LoopIndex		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Expression.py	NullLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NullLiteral.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Expression.py	EnumerationLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	EnumerationLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	EnumerationLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IntegerLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IntegerLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IntegerLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IntegerLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IntegerLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FloatingPointLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FloatingPointLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FloatingPointLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FloatingPointLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FloatingPointLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalLiteral.UnitName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalIntegerLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalIntegerLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalIntegerLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalIntegerLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalFloatingLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalFloatingLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalFloatingLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	PhysicalFloatingLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	CharacterLiteral.__init__		100%	13	0	0		100%	6	0		100%
pyVHDLModel/Expression.py	CharacterLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	CharacterLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	CharacterLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	CharacterLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	StringLiteral.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	StringLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	StringLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	StringLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	StringLiteral.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.__init__		100%	23	0	0		100%	10	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.Value		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.BinaryValue		100%	68	0	0		100%	38	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.Bits		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.Length		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.IsSigned		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BitStringLiteral.__str__		92%	13	1	0		80%	10	2		87%
pyVHDLModel/Expression.py	ParenthesisExpression.Operand		0%	1	1	0		100%	0	0		0%
pyVHDLModel/Expression.py	UnaryExpression.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	UnaryExpression.Operand		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	UnaryExpression.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	UnaryExpression.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	UnaryExpression.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NegationExpression.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IdentityExpression.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TypeConversion.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TypeConversion.TargetSubtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TypeConversion.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TypeConversion.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TypeConversion.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubExpression.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BinaryExpression.__init__		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BinaryExpression.LeftOperand		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BinaryExpression.RightOperand		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BinaryExpression.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	BinaryExpression.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangeExpression.Direction		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangeExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	AddingExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	MultiplyingExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	ExponentiationExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	LogicalExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RelationalExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	ShiftExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.__init__		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.Operand		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.Subtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpression.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TernaryExpression.__init__		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	TernaryExpression.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.ThenValue		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.Condition		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.ElseValue		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	WhenElseExpression.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	FunctionCall.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubtypeAllocation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubtypeAllocation.Subtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubtypeAllocation.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubtypeAllocation.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SubtypeAllocation.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpressionAllocation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpressionAllocation.QualifiedExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpressionAllocation.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpressionAllocation.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	QualifiedExpressionAllocation.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	AggregateElement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	AggregateElement.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	AggregateElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SimpleAggregateElement.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	SimpleAggregateElement.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IndexedAggregateElement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IndexedAggregateElement.Index		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IndexedAggregateElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IndexedAggregateElement.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	IndexedAggregateElement.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangedAggregateElement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangedAggregateElement.Range		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangedAggregateElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangedAggregateElement.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	RangedAggregateElement.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NamedAggregateElement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NamedAggregateElement.Name		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NamedAggregateElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NamedAggregateElement.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	NamedAggregateElement.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	OthersAggregateElement.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	OthersAggregateElement.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	Aggregate.__init__		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Expression.py	Aggregate.Elements		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	Aggregate.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	Aggregate.Visit		100%	6	0	0		100%	4	0		100%
pyVHDLModel/Expression.py	Aggregate.__str__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Expression.py	(no function)		99%	529	1	0		50%	2	1		99%
pyVHDLModel/Formatting/VHDL.py	VHDLStyle.__init__		100%	25	0	0		100%	14	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLStyle.KeywordCase		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLStyle.IndentStyle		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLStyle.IndentSize		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.__init__		100%	12	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.Style		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.Format		100%	12	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitLeftParenthesis		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._Write		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitComma		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitArrow		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitApostrophe		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitWhen		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._Keyword		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._Keywords		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitElse		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOperator		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitDirection		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitNullLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEnumerationLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIntegerLiteral		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._Enter		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIntegerLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._Leave		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFloatingPointLiteral		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFloatingPointLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._PrecedenceOfReal		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._FormatReal		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPhysicalIntegerLiteral		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPhysicalIntegerLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPhysicalFloatingLiteral		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPhysicalFloatingLiteral		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitCharacterLiteral		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._IsGraphic		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitStringLiteral		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBitStringLiteral		83%	18	3	0		90%	10	1		86%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitUnaryExpression		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartUnaryExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitNegationExpression		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartNegationExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIdentityExpression		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIdentityExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartTypeConversion		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSubExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSubExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitLogicalExpression		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartLogicalExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRelationalExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRelationalExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitShiftExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartShiftExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAddingExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAddingExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitMultiplyingExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartMultiplyingExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitExponentiationExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartExponentiationExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRangeExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRangeExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitWhenElseExpression		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartWhenElseExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartQualifiedExpression		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSubtypeAllocation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitQualifiedExpressionAllocation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAggregate		100%	9	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAggregate		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIndexedAggregateElement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOthersAggregateElement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSimpleRange		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSimpleRange		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRangeFromName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRangeFromName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSimpleName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSelectedName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAllName		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAttributeName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIndexedName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartParenthesisName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSlicedName		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOpenName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAssociationItem		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSemicolon		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteIndentation		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitVariableAssignment		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIs		100%	7	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRangeConstraint		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIndexConstraint		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIndexConstraint		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRecordConstraint		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRecordConstraint		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericClause		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartGenericClause		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteClosingParenthesis		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPortClause		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPortClause		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConstant		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteObjectDeclaration		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConstant		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitDeferredConstant		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartDeferredConstant		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitVariable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartVariable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSharedVariable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSharedVariable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSignal		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSignal		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFile		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFile		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericConstantInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteInterfaceItem		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericTypeInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPortSimpleSignalInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPortViewSignalInterfaceItem		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitParameterConstantInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitParameterVariableInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitParameterSimpleSignalInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitParameterViewSignalInterfaceItem		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitParameterFileInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitModeViewDeclaration		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartModeViewDeclaration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteEnd		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteEndLine		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSimpleModeViewElement		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitCompositeModeViewElement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartCompositeModeViewElement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitComponent		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartComponent		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBox		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOf		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitUnits		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSecondaryUnitDeclaration		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSecondaryUnitDeclaration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntitySpecification		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartEntitySpecification		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAnonymousType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSubtype		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSubtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEnumeratedType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteTypeHeader		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartEnumeratedType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIntegerType		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIntegerType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRealType		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRealType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPhysicalType		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPhysicalType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitArrayType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartArrayType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRecordType		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRecordType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRecordTypeElement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartRecordTypeElement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAccessType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAccessType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFileType		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFileType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAlias		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAlias		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAttribute		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAttribute		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAttributeSpecification		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartAttributeSpecification		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBegin		100%	11	0	0		100%	8	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._IsSubprogramBody		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitReturn		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFormalParameterList		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFormalParameterList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericMapAspect		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteMapAspect		100%	7	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartGenericMapAspect		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteMapAspectEnd		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitProcedure		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartProcedure		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFunction		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteFunctionDesignator		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFunction		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericProcedureInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenericFunctionInterfaceItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitProcedureInstantiation		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartProcedureInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFunctionInstantiation		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartFunctionInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitProtectedType		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartProtectedType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitProtectedTypeBody		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartProtectedTypeBody		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPortMapAspect		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPortMapAspect		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitContextClause		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartContextClause		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitLibraryClause		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartLibraryClause		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitUseClause		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartUseClause		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitContextReference		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartContextReference		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitContext		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteUnitHeader		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartContext		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPackage		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPackage		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPackageBody		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPackageBody		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitPackageInstantiation		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartPackageInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartEntity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitArchitecture		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartArchitecture		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConfiguration		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConfiguration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBlockConfiguration		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartBlockSpecification		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartBlockConfiguration		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitComponentConfiguration		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartInstantiationList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartComponentConfiguration		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBindingIndication		100%	5	0	0		50%	2	1		86%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartBindingIndication		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntityAspectEntity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntityAspectConfiguration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntityAspectOpen		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAllInstantiationList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOthersInstantiationList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSignalAssignment		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitAfter		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSelect		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitBar		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitReport		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSeverity		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSensitivityList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSensitivityList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitActualParameterPart		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartActualParameterPart		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartOthersSelectedWaveform		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIndexedChoice		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitProcessStatement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteStatementStart		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartProcessStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentProcedureCall		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentProcedureCall		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentSimpleSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentSimpleSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentSelectedSignalAssignment		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentSelectedSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentConditionalSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentConditionalSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentAssertStatement		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentAssertStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitRightParenthesis		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenerate		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitComponentInstantiation		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartComponentInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEntityInstantiation		75%	4	1	0		50%	2	1		67%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartEntityInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConfigurationInstantiation		75%	4	1	0		50%	2	1		67%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConfigurationInstantiation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitConcurrentBlockStatement		80%	5	1	0		50%	2	1		71%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartConcurrentBlockStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIfGenerateStatement		67%	3	1	0		50%	2	1		60%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIfGenerateStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIfGenerateBranch		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter._WriteAlternativeLabel		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIfGenerateBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitElsifGenerateBranch		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartElsifGenerateBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitElseGenerateBranch		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartElseGenerateBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitCaseGenerateStatement		80%	5	1	0		50%	2	1		71%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartCaseGenerateStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitGenerateCase		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartGenerateCase		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOthersGenerateCase		80%	5	1	0		50%	2	1		71%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartOthersGenerateCase		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIndexedGenerateChoice		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitForGenerateStatement		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartForGenerateStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOn		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitUntil		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitFor		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartOthersSelectedExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialProcedureCall		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialProcedureCall		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialSimpleSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialSimpleSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialVariableAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialVariableAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialConditionalVariableAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialConditionalVariableAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialConditionalSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialConditionalSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialSelectedVariableAssignment		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialSelectedVariableAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialSelectedSignalAssignment		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialSelectedSignalAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSignalForceAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSignalForceAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSignalReleaseAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSignalReleaseAssignment		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialReportStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialReportStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitSequentialAssertStatement		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartSequentialAssertStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitNullStatement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitReturnStatement		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartReturnStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitWaitStatement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartWaitStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitThen		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitLoop		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIfStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIfStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitIfBranch		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartIfBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitElsifBranch		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartElsifBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitElseBranch		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartElseBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitCaseStatement		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartCaseStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitCase		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartCase		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitOthersCase		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartOthersCase		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitEndlessLoopStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartEndlessLoopStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitForLoopStatement		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartForLoopStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitWhileLoopStatement		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartWhileLoopStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitNextStatement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartNextStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.VisitExitStatement		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	VHDLWriter.DepartExitStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Formatting/VHDL.py	(no function)		100%	390	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Ieee.__init__		85%	13	2	0		80%	10	2		83%
pyVHDLModel/IEEE.py	Ieee.Flavor		0%	1	1	0		100%	0	0		0%
pyVHDLModel/IEEE.py	Ieee.LoadSynopsysPackages		75%	4	1	0		50%	2	1		67%
pyVHDLModel/IEEE.py	Ieee.LoadMentorGraphicsPackages		75%	4	1	0		50%	2	1		67%
pyVHDLModel/IEEE.py	Ieee.LoadVITALPackages		0%	2	2	0		100%	0	0		0%
pyVHDLModel/IEEE.py	Math_Complex.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Math_Complex_Body.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_1164.__init__		100%	16	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_TextIO.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Numeric_Bit.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Numeric_Bit_Unsigned_Body.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Numeric_Std.__init__		100%	18	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Numeric_Std_Unsigned.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Numeric_Std_Unsigned_Body.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Fixed_Generic_Pkg.__init__		100%	6	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Fixed_Generic_Pkg_Body.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Fixed_Pkg.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Float_Generic_Pkg.__init__		100%	6	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Float_Pkg.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_Arith_MentorGraphics.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_Arith_Body_MentorGraphics.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	VITAL_Timing.__init__		0%	3	3	0		100%	0	0		0%
pyVHDLModel/IEEE.py	VITAL_Timing_Body.__init__		0%	3	3	0		100%	0	0		0%
pyVHDLModel/IEEE.py	VITAL_Primitives.__init__		0%	4	4	0		100%	0	0		0%
pyVHDLModel/IEEE.py	VITAL_Primitives_Body.__init__		0%	3	3	0		100%	0	0		0%
pyVHDLModel/IEEE.py	VITAL_Memory.__init__		0%	7	7	0		100%	0	0		0%
pyVHDLModel/IEEE.py	VITAL_Memory_Body.__init__		0%	7	7	0		100%	0	0		0%
pyVHDLModel/IEEE.py	Std_Logic_Arith_Synopsys.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_Misc.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_Signed.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_TextIO_Synopsys.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	Std_Logic_Unsigned.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/IEEE.py	(no function)		100%	120	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	GenericInstantiationMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	GenericEntityInstantiationMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	SubprogramInstantiationMixin.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	SubprogramInstantiationMixin.SubprogramReference		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	ProcedureInstantiation.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	ProcedureInstantiation.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	FunctionInstantiation.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	FunctionInstantiation.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	FunctionInstantiation.ReturnType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	PackageInstantiation.__init__		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	PackageInstantiation.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	PackageInstantiation.PackageReference		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Instantiation.py	PackageInstantiation.Instantiate		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Instantiation.py	(no function)		98%	42	1	0		50%	2	1		95%
pyVHDLModel/Interface.py	ModeViewElement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	ModeViewElement.__str__		0%	1	1	0		100%	0	0		0%
pyVHDLModel/Interface.py	SimpleModeViewElement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	SimpleModeViewElement.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	SimpleModeViewElement.Mode		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	SimpleModeViewElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	CompositeModeViewElement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	CompositeModeViewElement.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	CompositeModeViewElement.ModeViewName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	CompositeModeViewElement.Copy		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Interface.py	ModeViewDeclaration.__init__		100%	10	0	0		100%	4	0		100%
pyVHDLModel/Interface.py	ModeViewDeclaration.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Interface.py	ModeViewDeclaration.Subtype		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Object.py	File.Visit		100%	3	0	0		100%	0	0		100%
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pyVHDLModel/Regions.py	WithGenericsMixin.GenericCount		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Regions.py	WithGenericsMixin.MoveGenericItem		100%	33	0	0		100%	20	0		100%
pyVHDLModel/Regions.py	WithGenericsMixin._IndexGenericItems		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	WithGenericsMixin._VisitGenericClause		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	WithPortsMixin.__init__		100%	5	0	0		100%	4	0		100%
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pyVHDLModel/Regions.py	WithPortsMixin.PortCount		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	WithPortsMixin.IterateSinglePortDeclarations		100%	7	0	0		100%	10	0		100%
pyVHDLModel/Regions.py	WithPortsMixin.AddPortItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	WithPortsMixin.InsertPortItem		88%	32	4	0		86%	14	2		87%
pyVHDLModel/Regions.py	WithPortsMixin.RemovePortItem		100%	15	0	0		88%	8	1		96%
pyVHDLModel/Regions.py	WithPortsMixin.MovePortItem		84%	25	4	0		86%	14	2		85%
pyVHDLModel/Regions.py	WithPortsMixin._IndexPortItems		100%	3	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	WithPortsMixin._VisitPortClause		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.__init__		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.ParameterItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.ParameterCount		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.IterateSingleParameterDeclarations		100%	7	0	0		100%	10	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.AddParameterItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.InsertParameterItem		88%	33	4	0		86%	14	2		87%
pyVHDLModel/Regions.py	WithParametersMixin.RemoveParameterItem		100%	16	0	0		100%	8	0		100%
pyVHDLModel/Regions.py	WithParametersMixin.MoveParameterItem		85%	26	4	0		86%	14	2		85%
pyVHDLModel/Regions.py	WithParametersMixin._IndexParameterItems		100%	3	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	WithParametersMixin._VisitFormalParameterList		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._AddToNamespace		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._RemoveFromNamespace		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._RemoveDeclaredItemsFromNamespace		100%	4	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._RemoveDeclaredItemEntries		100%	8	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._IndexOverload		100%	6	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._UnindexOverload		100%	8	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._AddOverloadToNamespace		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._RemoveOverloadFromNamespace		100%	10	0	0		100%	6	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._SharedRegions		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._MayShareIdentifier		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._ClashingDeclarations		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin._DeclaredItemsSharingIdentifiers		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin.AddDeclaredItem		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin.InsertDeclaredItem		100%	61	0	0		100%	38	0		100%
pyVHDLModel/Regions.py	DeclarationRegionMixin.InsertDeclaredItemBefore		100%	14	0	0		90%	10	1		96%
pyVHDLModel/Regions.py	DeclarationRegionMixin.InsertDeclaredItemAfter		93%	14	1	0		90%	10	1		92%
pyVHDLModel/Regions.py	DeclarationRegionMixin.RemoveDeclaredItem		100%	23	0	0		93%	14	1		97%
pyVHDLModel/Regions.py	DeclarationRegionMixin.MoveDeclaredItem		100%	41	0	0		96%	26	1		99%
pyVHDLModel/Regions.py	DeclarationRegionMixin.MoveDeclaredItemBefore		100%	15	0	0		90%	10	1		96%
pyVHDLModel/Regions.py	DeclarationRegionMixin.MoveDeclaredItemAfter		80%	15	3	0		80%	10	2		80%
pyVHDLModel/Regions.py	DeclarationRegionMixin._VisitDeclaredItems		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	WithoutStatementsMixin._Labels		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.__init__		100%	16	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.DeclaredItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Types		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Subtypes		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Constants		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Signals		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.SharedVariables		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Files		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Functions		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Procedures		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.Components		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin._Declarations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin.IndexDeclaredItems		100%	13	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin._IndexDeclaredItem		100%	40	0	0		100%	30	0		100%
pyVHDLModel/Regions.py	ConcurrentDeclarationRegionMixin._UnindexDeclaredItem		79%	24	5	0		75%	20	5		77%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.__init__		100%	14	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.DeclaredItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Namespace		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Types		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Subtypes		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Constants		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Variables		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Files		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Functions		0%	1	1	0		100%	0	0		0%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.Procedures		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin._Declarations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin.IndexDeclaredItems		100%	11	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin._IndexDeclaredItem		90%	29	3	0		91%	22	2		90%
pyVHDLModel/Regions.py	SequentialDeclarationRegionMixin._UnindexDeclaredItem		59%	17	7	0		50%	14	5		55%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin.__init__		100%	9	0	0		100%	4	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin.DeclaredItems		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin.Functions		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin.Procedures		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin._Declarations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin.IndexDeclaredItems		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin._IndexDeclaredItem		88%	8	1	0		75%	4	1		83%
pyVHDLModel/Regions.py	ProtectedTypeDeclarationRegionMixin._UnindexDeclaredItem		75%	4	1	0		50%	2	1		67%
pyVHDLModel/Regions.py	(no function)		98%	182	3	0		50%	2	1		98%
pyVHDLModel/STD.py	Std.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/STD.py	Standard.__init__		100%	60	0	0		100%	0	0		100%
pyVHDLModel/STD.py	Env.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/STD.py	(no function)		100%	25	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.__init__		100%	5	0	0		100%	4	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.Statements		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin._VisitStatements		100%	2	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin._Labels		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin._LabelsOf		85%	13	2	0		83%	12	2		84%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.AddStatement		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.InsertStatement		100%	33	0	0		100%	18	0		100%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.InsertStatementBefore		71%	14	4	0		70%	10	3		71%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.InsertStatementAfter		64%	14	5	0		60%	10	4		62%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.RemoveStatement		100%	15	0	0		80%	10	2		92%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.MoveStatement		85%	26	4	0		81%	16	3		83%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.MoveStatementBefore		47%	15	8	0		40%	10	4		44%
pyVHDLModel/Sequential.py	SequentialStatementsMixin.MoveStatementAfter		67%	15	5	0		70%	10	3		68%
pyVHDLModel/Sequential.py	SequentialProcedureCall.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialProcedureCall.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSignalAssignment.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSimpleSignalAssignment.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSimpleSignalAssignment.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialVariableAssignment.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialVariableAssignment.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialConditionalVariableAssignment.__init__		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	SequentialConditionalVariableAssignment.Visit		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Sequential.py	SequentialConditionalVariableAssignment.ConditionalExpressions		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialConditionalSignalAssignment.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialConditionalSignalAssignment.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSelectedVariableAssignment.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSelectedVariableAssignment.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSelectedSignalAssignment.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialSelectedSignalAssignment.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SignalForceAssignment.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SignalForceAssignment.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SignalReleaseAssignment.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SignalReleaseAssignment.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialReportStatement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialReportStatement.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialAssertStatement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialAssertStatement.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	Branch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	Branch._LabelRegion		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	IfBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IfBranch.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ElsifBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ElsifBranch.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ElseBranch.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ElseBranch.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IfStatement.__init__		100%	12	0	0		100%	6	0		100%
pyVHDLModel/Sequential.py	IfStatement.Visit		100%	7	0	0		100%	4	0		100%
pyVHDLModel/Sequential.py	IfStatement.IfBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IfStatement.ElsIfBranches		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IfStatement.ElseBranch		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IndexedChoice.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IndexedChoice.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IndexedChoice.Expression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	IndexedChoice.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	RangedChoice.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	RangedChoice.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	RangedChoice.Range		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	RangedChoice.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialCase.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	SequentialCase._LabelRegion		75%	4	1	0		50%	2	1		67%
pyVHDLModel/Sequential.py	Case.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	Case.Visit		100%	8	0	0		100%	4	0		100%
pyVHDLModel/Sequential.py	Case.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	OthersCase.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	OthersCase.__str__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	CaseStatement.__init__		100%	8	0	0		75%	4	1		92%
pyVHDLModel/Sequential.py	CaseStatement.Visit		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	CaseStatement.SelectExpression		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	CaseStatement.Cases		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	LoopStatement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	LoopStatement._LabelRegion		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	EndlessLoopStatement.Visit		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ForLoopStatement.__init__		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ForLoopStatement.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ForLoopStatement.LoopIndex		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ForLoopStatement.Range		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	WhileLoopStatement.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	WhileLoopStatement.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	LoopControlStatement.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	LoopControlStatement.LoopReference		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	NextStatement.Visit		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	ExitStatement.Visit		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	NullStatement.Visit		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	ReturnStatement.__init__		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	ReturnStatement.Visit		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Sequential.py	ReturnStatement.ReturnValue		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	WaitStatement.__init__		100%	11	0	0		100%	6	0		100%
pyVHDLModel/Sequential.py	WaitStatement.Visit		100%	14	0	0		100%	10	0		100%
pyVHDLModel/Sequential.py	WaitStatement.SensitivityList		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	WaitStatement.Timeout		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Sequential.py	(no function)		99%	213	1	0		50%	2	1		99%
pyVHDLModel/Subprogram.py	SubprogramSignature.__init__		100%	24	0	0		100%	12	0		100%
pyVHDLModel/Subprogram.py	SubprogramSignature.ParameterTypes		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	SubprogramSignature.ReturnType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	SubprogramSignature.ParameterTypeNames		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	SubprogramSignature.ReturnTypeName		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	SubprogramSignature.__str__		100%	5	0	0		100%	2	0		100%
pyVHDLModel/Subprogram.py	Subprogram.__init__		100%	9	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram.Parent		100%	4	0	0		100%	2	0		100%
pyVHDLModel/Subprogram.py	Subprogram.IsPure		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram.Signature		100%	3	0	0		50%	2	1		80%
pyVHDLModel/Subprogram.py	Subprogram._ParameterItemsChanged		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram.IndexDeclaredItems		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram._Declarations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram._LabelRegion		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram._VisitDeclarativeAndStatementPart		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Subprogram.__str__		0%	2	2	0		100%	0	0		0%
pyVHDLModel/Subprogram.py	Procedure.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Procedure.Visit		100%	5	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Function.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Function.Visit		100%	7	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Function.ReturnType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	Function.Signature		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Subprogram.py	MethodMixin.__init__		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Subprogram.py	MethodMixin.ProtectedType		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	ProcedureMethod.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	FunctionMethod.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Subprogram.py	(no function)		99%	72	1	0		50%	2	1		97%
pyVHDLModel/Symbol.py	Symbol.__init__		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.Name		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.Reference		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.IsResolved		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.__bool__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	Symbol.__repr__		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Symbol.py	Symbol.__str__		100%	3	0	0		100%	2	0		100%
pyVHDLModel/Symbol.py	LibraryReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	LibraryReferenceSymbol.Library		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	LibraryReferenceSymbol.Library		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	LibraryReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageReferenceSymbol.Package		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageReferenceSymbol.Package		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ModeViewSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ModeViewSymbol.ModeView		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ModeViewSymbol.ModeView		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ModeViewSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubprogramReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubprogramReferenceSymbol.Subprogram		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubprogramReferenceSymbol.Subprogram		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubprogramReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationSymbol.Configuration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationSymbol.Configuration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	VariableSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	VariableSymbol.Variable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	VariableSymbol.Variable		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	VariableSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SignalSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SignalSymbol.Signal		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SignalSymbol.Signal		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SignalSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ContextReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ContextReferenceSymbol.Context		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ContextReferenceSymbol.Context		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ContextReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageMemberReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageMemberReferenceSymbol.Member		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageMemberReferenceSymbol.Member		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageMemberReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	AllPackageMembersReferenceSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	AllPackageMembersReferenceSymbol.Members		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	AllPackageMembersReferenceSymbol.Members		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	AllPackageMembersReferenceSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntityInstantiationSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntityInstantiationSymbol.Entity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntityInstantiationSymbol.Entity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntityInstantiationSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ComponentInstantiationSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ComponentInstantiationSymbol.Component		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ComponentInstantiationSymbol.Component		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ComponentInstantiationSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationInstantiationSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationInstantiationSymbol.Configuration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationInstantiationSymbol.Configuration		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConfigurationInstantiationSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntitySymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntitySymbol.Entity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntitySymbol.Entity		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	EntitySymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArchitectureSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArchitectureSymbol.Architecture		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArchitectureSymbol.Architecture		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArchitectureSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageSymbol.Package		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageSymbol.Package		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	PackageSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RecordElementSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RecordElementSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RangeAttributeSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RangeAttributeSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubtypeSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubtypeSymbol.TypeMark		100%	6	0	0		100%	2	0		100%
pyVHDLModel/Symbol.py	SubtypeSymbol.Subtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubtypeSymbol.Subtype		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SubtypeSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ScalarConstraint.__init__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Symbol.py	ConstrainedScalarSubtypeSymbol.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedScalarSubtypeSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedScalarSubtypeSymbol.Visit		100%	6	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArrayConstraint.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ArrayConstraint.Constraints		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RecordConstraint.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	RecordConstraint.Constraints		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedArraySubtypeSymbol.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedArraySubtypeSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedArraySubtypeSymbol.Visit		100%	9	0	0		100%	4	0		100%
pyVHDLModel/Symbol.py	ConstrainedRecordSubtypeSymbol.__init__		100%	2	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedRecordSubtypeSymbol.Copy		100%	4	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	ConstrainedRecordSubtypeSymbol.Visit		100%	12	0	0		100%	4	0		100%
pyVHDLModel/Symbol.py	SimpleObjectOrFunctionCallSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	SimpleObjectOrFunctionCallSymbol.Copy		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	IndexedObjectOrFunctionCallSymbol.__init__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Symbol.py	IndexedObjectOrFunctionCallSymbol.Copy		100%	3	0	0		100%	0	0		100%
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pyVHDLModel/Type.py	Subtype.ResolutionFunction		100%	1	0	0		100%	0	0		100%
pyVHDLModel/Type.py	Subtype.Visit		100%	3	0	0		100%	0	0		100%
pyVHDLModel/Type.py	Subtype.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Type.py	EnumeratedType.Visit		100%	6	0	0		100%	4	0		100%
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pyVHDLModel/Type.py	IntegerType.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Type.py	RealType.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Type.py	PhysicalType.Visit		100%	8	0	0		100%	2	0		100%
pyVHDLModel/Type.py	PhysicalType.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/Type.py	ArrayType.__str__		100%	1	0	0		100%	0	0		100%
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pyVHDLModel/__init__.py	Design.ImportObjects._ImportObjects		0%	12	12	0		0%	14	0		0%
pyVHDLModel/__init__.py	Design.CreateTypeAndObjectGraph		0%	11	11	0		0%	8	0		0%
pyVHDLModel/__init__.py	Design.CreateTypeAndObjectGraph._HandlePackage		0%	36	36	0		0%	14	0		0%
pyVHDLModel/__init__.py	Design.CreateTypeAndObjectGraph._LinkSymbolsInExpression		0%	13	13	0		0%	8	0		0%
pyVHDLModel/__init__.py	Design.CreateTypeAndObjectGraph._LinkItems		0%	32	32	0		0%	20	0		0%
pyVHDLModel/__init__.py	Design.LinkContexts		77%	44	10	0		72%	18	3		76%
pyVHDLModel/__init__.py	Design.LinkArchitectures		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.LinkPackageBodies		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.LinkPackageInstances		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.LinkLibraryReferences		86%	42	6	0		89%	18	2		87%
pyVHDLModel/__init__.py	Design.LinkPackageReferences		78%	55	12	0		82%	38	5		80%
pyVHDLModel/__init__.py	Design.LinkContextReferences		81%	32	6	0		82%	22	2		81%
pyVHDLModel/__init__.py	Design.LinkComponents		89%	9	1	0		75%	4	1		85%
pyVHDLModel/__init__.py	Design._IterateComponents		89%	9	1	0		88%	8	1		88%
pyVHDLModel/__init__.py	Design._IterateComponents.iterateStatements		25%	20	15	0		38%	16	4		31%
pyVHDLModel/__init__.py	Design._IterateComponents.iterateDeclaredItems		0%	3	3	0		0%	4	0		0%
pyVHDLModel/__init__.py	Design.LinkInstantiations		73%	45	12	0		75%	20	1		74%
pyVHDLModel/__init__.py	Design.IndexPackages		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.IndexPackageBodies		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.IndexEntities		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.IndexArchitectures		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Design.CreateHierarchyGraph		100%	17	0	0		100%	12	0		100%
pyVHDLModel/__init__.py	Design.ComputeCompileOrder		100%	14	0	0		100%	6	0		100%
pyVHDLModel/__init__.py	Design.ComputeCompileOrder.predicate		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Design.IterateDocumentsInCompileOrder		0%	4	4	0		0%	4	0		0%
pyVHDLModel/__init__.py	Design.GetUnusedDesignUnits		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Design.__repr__		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Library.__init__		100%	11	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Documentation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Documentation		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Contexts		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Configurations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Entities		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Architectures		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.Packages		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.PackageBodies		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Library.DependencyVertex		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Library.IterateDesignUnits		100%	19	0	0		100%	26	0		100%
pyVHDLModel/__init__.py	Library.LinkArchitectures		77%	13	3	0		75%	8	2		76%
pyVHDLModel/__init__.py	Library.LinkPackageBodies		89%	9	1	0		75%	4	1		85%
pyVHDLModel/__init__.py	Library.LinkPackageInstances		68%	25	8	0		60%	10	2		66%
pyVHDLModel/__init__.py	Library.IndexPackages		100%	3	0	0		75%	4	1		86%
pyVHDLModel/__init__.py	Library.IndexPackageBodies		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Library.IndexEntities		100%	2	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Library.IndexArchitectures		100%	4	0	0		100%	4	0		100%
pyVHDLModel/__init__.py	Library.__repr__		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.__init__		100%	23	0	0		100%	4	0		100%
pyVHDLModel/__init__.py	Document.Visit		100%	4	0	0		100%	2	0		100%
pyVHDLModel/__init__.py	Document._AddEntity		60%	10	4	0		50%	4	2		57%
pyVHDLModel/__init__.py	Document._AddArchitecture		81%	16	3	0		75%	4	1		80%
pyVHDLModel/__init__.py	Document._AddPackage		60%	10	4	0		50%	4	2		57%
pyVHDLModel/__init__.py	Document._AddPackageBody		60%	10	4	0		50%	4	2		57%
pyVHDLModel/__init__.py	Document._AddContext		60%	10	4	0		50%	4	2		57%
pyVHDLModel/__init__.py	Document._AddConfiguration		60%	10	4	0		50%	4	2		57%
pyVHDLModel/__init__.py	Document._AddVerificationUnit		0%	10	10	0		0%	4	0		0%
pyVHDLModel/__init__.py	Document._AddVerificationProperty		0%	10	10	0		0%	4	0		0%
pyVHDLModel/__init__.py	Document._AddVerificationMode		0%	10	10	0		0%	4	0		0%
pyVHDLModel/__init__.py	Document._AddDesignUnit		52%	25	12	0		60%	20	2		56%
pyVHDLModel/__init__.py	Document.AddDesignUnit		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.InsertDesignUnit		78%	85	19	0		73%	64	5		76%
pyVHDLModel/__init__.py	Document.RemoveDesignUnit		69%	55	17	0		52%	44	7		62%
pyVHDLModel/__init__.py	Document.Path		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.VHDLVersion		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Document.Library		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.DesignUnits		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.Contexts		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.Configurations		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.Entities		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.Architectures		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.Packages		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.PackageBodies		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.VerificationUnits		100%	1	0	0		100%	0	0		100%
pyVHDLModel/__init__.py	Document.VerificationProperties		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Document.VerificationModes		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Document.CompileOrderVertex		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	Document.IterateDesignUnits		100%	19	0	0		77%	26	6		87%
pyVHDLModel/__init__.py	Document.__repr__		0%	1	1	0		100%	0	0		0%
pyVHDLModel/__init__.py	(no function)		99%	331	1	0		50%	2	1		99%
Total			93%	10982	724	9		82%	2346	246		91%

No items found using the specified filter.

393 empty functions skipped.